Switch circuit of cascode type having high speed switching performance

Patent metadata

Field	Value
Publication number	US-2016247792-A1
Application number	US-201514815378-A
Country	US
Kind code	A1
Filing date	Jul 31, 2015
Priority date	Feb 25, 2015
Publication date	Aug 25, 2016
Grant date	—

Abstract

Provided is switch circuit including first and second transistors, a source pad connected to a second node of the second transistor through a first signal path and connected to a gate node of the first transistor through a second signal path, a gate pad connected to a gate node of the second transistor through a third signal path; and a drain pad connected to a first node of the first transistor through a fourth signal path, wherein a second node of the first transistor and a first node of the second transistor are connected to each other through a fifth signal path, and the gate node of the first transistor and the second node of the second transistor are connected to each other through a sixth signal path separated from the first and second signal paths.

First claim

What is claimed is:

1 . A switch circuit comprising:
first and second transistors; a source pad connected to a second node of the second transistor through a first signal path and connected to a gate node of the first transistor through a second signal path; a gate pad connected to a gate node of the second transistor through a third signal path; and a drain pad connected to a first node of the first transistor through a fourth signal path, wherein a second node of the first transistor and a first node of the second transistor are connected to each other through a fifth signal path, and the gate node of the first transistor and the second node of the second transistor are connected to each other through a sixth signal path separated from the first and second signal paths.

2 . The switch circuit of claim 1 , wherein the second transistor comprises:
a conductive plate on a substrate; a drain terminal disposed on the conductive plate and electrically connected to the conductive plate, the drain terminal forming the first node of the second transistor; a first active area on the drain terminal; a gate terminal in a first portion on the first active area, the gate terminal forming the gate node of the second transistor; and a source terminal in a second portion of the first active area, the source terminal forming the second node of the second transistor.

3 . The switch circuit of claim 2 , wherein the first signal path comprises an interconnection connecting the source terminal of the second transistor and the source pad, and
the third signal path comprises an interconnection connecting the gate terminal of the second transistor and the source pad.

4 . The switch circuit of claim 2 , wherein the first transistor comprises:
a second active area in a second portion on the substrate; a gate terminal in a first portion on the second active area, the gate terminal of the first transistor forming the gate node of the first transistor; a drain terminal in a second portion on the second active area, the drain terminal of the first transistor forming the first node of the first transistor; and a source terminal in a third portion of the second active area, the source terminal of the first transistor forming the second node of the first transistor.

5 . The switch circuit of claim 4 , wherein the second signal path comprises an interconnection connecting the gate terminal of the first transistor and the source pad, and
the fourth signal path comprises an interconnection connecting the drain terminal of the first transistor and the drain pad.

6 . The switch circuit of claim 4 , wherein the fifth signal path comprises an interconnection connecting the source terminal of the first transistor and the conductive plate.

7 . The switch circuit of claim 4 , wherein the sixth signal path comprises an interconnection connecting the gate terminal of the first transistor and the source terminal of the second transistor.

8 . The switch circuit of claim 2 , wherein the first transistor comprises:
a second active area in a second portion of the conductive plate; a gate terminal in a first portion on the second active area, the gate terminal of the first transistor forming the gate node of the first transistor; a drain terminal in a second portion on the second active area, the drain terminal of the first transistor forming the first node of the first transistor; and a source terminal in a third portion of the second active area, the source terminal of the first transistor forming the second node of the first transistor.

9 . The switch circuit of claim 8 , wherein the fifth signal path comprises an interconnection connecting the source terminal of the first transistor and the conductive plate.

10 . The switch circuit of claim 8 , wherein the fifth signal path comprises via contact penetrating the second active area to contact the source terminal of the first transistor and the conductive plate.

11 . The switch circuit of claim 1 , wherein the first transistor comprises a gallium nitride (GaN) transistor of a normally-on type.

12 . The switch circuit of claim 1 , wherein the second transistor comprises a metal oxide transistor (MOSFET) of a normally-off type.

13 . The switch circuit of claim 1 , further comprising a third transistor connected to the first transistor in parallel and commonly controlled with the first transistor.

14 . The switch circuit of claim 1 , further comprising a fourth transistor connected to the second transistor in parallel and commonly controlled with the second transistor.

Assignees

• Electronics & Telecommunications Res Inst

Inventors

• Chang Woojin

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/755

  between a chip and a laterally-adjacent insulating package substrate, interpose or RDL · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/811

  Multiple chips on leadframes · CPC title

• H10W72/50

  Bond wires · CPC title