System-on-chip including body bias voltage generator

Patent metadata

Field	Value
Publication number	US-9467135-B2
Application number	US-201514717379-A
Country	US
Kind code	B2
Filing date	May 20, 2015
Priority date	Aug 14, 2014
Publication date	Oct 11, 2016
Grant date	Oct 11, 2016

Abstract

A system-on-chip includes a body bias voltage generator having a voltage divider and a filter. The voltage divider includes a switched capacitor circuit and a resistor circuit. The switched capacitor circuit operates based on a first clock signal and a second clock signal. The resistor circuit outputs a first voltage through a first node, which is coupled to the switched capacitor circuit and the resistor circuit. The first and second clock signals have a same frequency. The filter performs a filtering operation on the first voltage to generate a body bias voltage.

First claim

What is claimed is:

1. A system-on-chip, comprising:
a body bias voltage generator which includes:
a voltage divider coupled between a supply voltage and a reference voltage, the voltage divider including a switched capacitor circuit to operate based on a first clock signal and a second clock signal and a resistor circuit, the voltage divider to output a first voltage through a first node coupled to the switched capacitor circuit and the resistor circuit, the first clock signal and a second clock signal to have a first frequency; and
a filter to perform a filtering operation on the first voltage to generate a body bias voltage, wherein the filter is to output a first body bias voltage when the switch capacitor circuit is set to a first resistance value and a second body bias voltage when the switch capacitor circuit is set to a second resistance value, the first and second body bias voltages corresponding to different operational frequencies of a system.

2. The system-on-chip as claimed in claim 1 , wherein the voltage divider is to:
increase a magnitude of the first voltage as the first frequency increases, and
decrease the magnitude of the first voltage as the first frequency decreases.

3. The system-on-chip as claimed in claim 1 , wherein:
the switched capacitor circuit is coupled between the supply voltage and the first node, and
the resistor circuit is coupled between the first node and the reference voltage.

4. The system-on-chip as claimed in claim 3 , wherein the body bias voltage is to be coupled to a p-type body on which an n-type metal oxide semiconductor transistor is formed.

5. The system-on-chip as claimed in claim 3 , wherein the switched capacitor circuit includes:
a first switch coupled between the supply voltage and a second node, the first switch to be turned on based on the first clock signal;
a second switch coupled between the second node and the first node, the second switch to be turned on based on the second clock signal; and
a capacitor coupled between the second node and the ground voltage.

6. The system-on-chip as claimed in claim 3 , wherein the resistor circuit includes:
first through n-th sub resistors coupled in series between the first node and the ground voltage, n being a positive integer; and
first through n-th sub switches coupled to the first through n-th sub resistors, respectively, in parallel, the first through n-th sub switches to be turned on based on first through n-th resistor control signals, respectively.

7. The system-on-chip as claimed in claim 3 , wherein the resistor circuit includes:
a first switch coupled between the first node and a second node, the first switch to be turned on based on the third clock signal;
a second switch coupled between the second node and the ground voltage, the second switch to be turned on based on the fourth clock signal; and
a capacitor coupled between the second node and the ground voltage.

8. The system-on-chip as claimed in claim 1 , wherein the voltage divider is to:
decrease a magnitude of the first voltage as the first frequency increases, and
increase the magnitude of the first voltage as the first frequency decreases.

9. The system-on-chip as claimed in claim 1 , wherein:
the switched capacitor circuit is coupled between the first node and the ground voltage, and
the resistor circuit is coupled between the supply voltage and the first node.

10. The system-on-chip as claimed in claim 9 , wherein the body bias voltage is to be coupled to an n-type body on which a p-type metal oxide semiconductor (PMOS) transistor is formed.

11. The system-on-chip as claimed in claim 9 , wherein the switched capacitor circuit includes:
a first switch coupled between the first node and a second node, the first switch to be turned on based on the first clock signal;
a second switch coupled between the second node and the ground voltage, the second switch to be turned on based on the second clock signal; and
a capacitor coupled between the second node and the ground voltage.

12. The system-on-chip as claimed in claim 9 , wherein the resistor circuit includes:
first through n-th sub resistors coupled in series between the supply voltage and the first node, n being a positive integer; and
first through n-th sub switches coupled to the first through n-th sub resistors, respectively, in parallel, the first through n-th sub switches to be turned on based on first through n-th resistor control signals, respectively.

13. The system-on-chip as claimed in claim 9 , wherein the resistor circuit includes:
a first switch coupled between the supply voltage and a second node, the first switch to be turned on based on the third clock signal;
a second switch coupled between the second node and the first node, the second switch to be turned on based on the fourth clock signal; and
a capacitor coupled between the second node and the ground voltage.

14. The system-on-chip as claimed in claim 1 , further comprising:
a buffer to buffer the body bias voltage generated by the filter and to output the body bias voltage.

15. The system-on-chip as claimed in claim 1 , wherein a resistance of the resistor circuit is to be varied based on a resistor control signal.

16. A system-on-chip, comprising:
a body bias voltage generator including:
a first switched capacitor circuit coupled between a supply voltage and a first node, the first switched capacitor circuit to operate based on a first clock signal and a second clock signal;
a first resistor circuit coupled between the first node and a ground voltage;
a first filter to perform a filtering operation on a first voltage received through the first node to generate a first body bias voltage;
a second resistor circuit coupled between the supply voltage and a second node;
a second switched capacitor circuit coupled between the second node and the ground voltage, the second switched capacitor circuit to operate based on the first clock signal and the second clock signal; and
a second filter to perform a filtering operation on a second voltage received through the second node to generate a second body bias voltage, wherein the first body bias voltage is to increase a threshold voltage of a transistor of a first conductivity type and the second body bias voltage is to decrease a threshold voltage of a transistor of a second conductivity type to set an operational speed of the system-on-chip.

17. A system-on-chip, comprising:
a system clock signal generator to generate a system clock signal having a first frequency based on a clock control signal;
a non-overlapping clock signal generator to generate a first clock signal and a second clock signal based on the system clock signal, the first clock signal and the second clock signal to have the first frequency, a time duration during which the first clock signal is activated to not overlap a time duration during which the second clock signal is activated;
a body bias voltage generator coupled between a supply voltage and a reference voltage, the body bias voltage generator to generate a first body bias voltage having a magnitude proportional to the first frequency and a second body bias voltage having a magnitude inversely proportional to the first frequency, the first and second bias voltages to be generated using a switched capacitor operating based on the first clock signal and the second clock signal; and
a processing block including at least one n-type metal oxide semiconductor transistor having a threshold voltage to vary based on the first body bias voltage and at least one p-type metal o

Assignees

• Kim Sang-Kyu
• Park Jae-Jin
• Lee Seung-Hoon
• Samsung Electronics Co Ltd

Inventors

• Kim Sang-Kyu
• Park Jae-Jin
• Lee Seung-Hoon

Classifications

• H03K17/04106 Primary

  in field-effect transistor switches (H03K17/0412, H03K17/0416 take precedence) · CPC title

• H03K2217/0018

  Special modifications or use of the back gate voltage of a FET · CPC title

• H03K17/145

  in field-effect transistor switches · CPC title

• H03K17/162

  without feedback from the output circuit to the control circuit · CPC title