Radio frequency current steering digital to analog converter

Patent metadata

Field	Value
Publication number	US-9432036-B1
Application number	US-201514847405-A
Country	US
Kind code	B1
Filing date	Sep 8, 2015
Priority date	Sep 8, 2015
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

In one example, a current steering circuit for a digital-to-analog converter (DAC) includes a source-coupled transistor pair responsive to a differential gate voltage; a current source coupled to the source-coupled transistor pair operable to source a bias current; a load circuit coupled to the source-coupled transistor pair operable to provide a differential output voltage; a driver having a first input, a second input, and a differential output, the differential output providing the differential gate voltage; and combinatorial logic having a data input, a clock input, a true output, and a complement output, the true output and the complement output respectively coupled to the first input and the second input of the driver, the combinatorial logic operable to exclusively OR a data signal on the data input and a clock signal on the clock input.

First claim

What is claimed is:

1. A current steering circuit for a digital-to-analog converter (DAC), comprising:
a source-coupled transistor pair responsive to a differential gate voltage;
a current source coupled to the source-coupled transistor pair operable to source a bias current;
a load circuit coupled to the source-coupled transistor pair operable to provide a differential output voltage;
a driver having a first input, a second input, and a differential output, the differential output providing the differential gate voltage; and
combinatorial logic having a data input, a clock input, a true output, and a complement output, the true output and the complement output respectively coupled to the first input and the second input of the driver, the combinatorial logic operable to exclusively OR a data signal on the data input and a clock signal on the clock input.

2. The current steering circuit of claim 1 , wherein the combinatorial logic includes an enable input operable to receive an enable signal, the combinatorial logic either performing the exclusive OR of the data signal and the clock signal or passing the data signal based on state of the enable signal.

3. The current steering circuit of claim 1 , further comprising:
an output transistor pair coupled between the source-coupled transistor pair and the load circuit.

4. The current steering circuit of claim 1 , wherein the transistors in the source-coupled transistor pair comprise n-channel metal oxide field effect transistors (MOSFETs).

5. The current steering circuit of claim 1 , wherein the transistors in the source-coupled transistor pair comprise p-channel metal oxide field effect transistors (MOSFETs).

6. The current steering circuit of claim 1 , wherein the data signal comprises a bit of a digital code input to the DAC.

7. The current steering circuit of claim 1 , wherein the combinatorial logic comprises an exclusive OR gate.

8. A digital-to-analog converter (DAC), comprising:
a decoder operable to output a data signal in response to binary input codes;
a plurality of output cells coupled between the decoder and a load circuit to provide an analog output signal centered at a carrier frequency, each of the plurality of output cells comprising:
a switch circuit coupled to the load circuit;
a driver having an input and an output, the output operable to control the switch; and
combinatorial logic having a data input operable to receive a respective bit of the data signal, a clock input operable to receive a clock signal, and an output, coupled to the input of the driver, the combinatorial logic operable to exclusively OR the data input and the clock input.

9. The DAC of claim 8 , wherein the combinatorial logic includes an enable input operable to receive an enable signal, the combinatorial logic either performing the exclusive OR of the data input and the clock input or passing the data input based on state of the enable signal.

10. The DAC of claim 8 , wherein the switch comprises a source-coupled transistor pair responsive to a differential gate voltage and a bias current, and wherein the output of the driver is a differential output providing the differential gate voltage.

11. The DAC of claim 10 , wherein the output of the combinatorial logic comprises a true output and a complement output.

12. The DAC of claim 10 , wherein each of the plurality of output cells further comprises:
an output transistor pair coupled between the source-coupled transistor pair and the load circuit.

13. The DAC of claim 10 , wherein the transistors in the source-coupled transistor pair comprise n-channel metal oxide field effect transistors (MOSFETs).

14. The DAC of claim 10 , wherein the transistors in the source-coupled transistor pair comprise p-channel metal oxide field effect transistors (MOSFETs).

15. The DAC of claim 10 , wherein the combinatorial logic comprises an exclusive OR gate.

16. A method of digital-to-analog conversion, comprising:
generating a data signal in response to binary input codes;
operating a plurality of output cells to provide an analog output signal centered at a carrier frequency, where each of the plurality of output cells is operated by:
exclusively ORing a respective bit of the data signal and a clock signal to generate a control signal; and
selectively driving a load circuit based on the control signal.

17. The method of claim 16 , wherein the operation of exclusively ORing the respective bit of the data signal and the clock signal is performed by combinatorial logic, and wherein the method further comprises enabling the combinatorial logic to perform the operation of exclusively ORing.

18. The method of claim 16 , wherein the operation of selectively driving comprises:
coupling the control signal to a driver; and
coupling output of the driver to a switch coupled to the load circuit.

19. The method of claim 18 , wherein the switch comprises a source-coupled transistor pair, and wherein the output of the driver comprises a differential gate voltage coupled to the source-coupled transistor pair.

20. The method of claim 19 , wherein the operation of selectively driving comprises steering a current through load circuit and the source-coupled transistor pair based on the differential gate voltage.

Assignees

• Xilinx Inc

Inventors

• Lowney Donnacha
• Erdmann Christophe

Classifications

• H03K17/04106 Primary

  in field-effect transistor switches (H03K17/0412, H03K17/0416 take precedence) · CPC title

• H03K19/21

  EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical · CPC title

• H03M1/747

  with equal currents which are switched by unary decoded digital signals · CPC title

• H03M1/66 Primary

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/002 Primary

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title