Method of manufacturing semiconductor device and semiconductor device

Patent metadata

Field	Value
Publication number	US-2025248057-A1
Application number	US-202519087645-A
Country	US
Kind code	A1
Filing date	Mar 24, 2025
Priority date	Sep 30, 2022
Publication date	Jul 31, 2025
Grant date	—

Abstract

A method of manufacturing a semiconductor device includes: forming a lower electrode on a substrate; forming, on the lower electrode, a high dielectric constant film made of an oxide containing a tetravalent metal cation; forming, on the high dielectric constant film, an oxide film made of an oxide containing a pentavalent metal cation; forming a mixed layer having conductivity, in which the oxide containing the tetravalent metal cation and the oxide containing the pentavalent metal cation are mixed, by causing the high dielectric constant film to react with the oxide film; and forming an upper electrode.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor device, the method comprising:
forming a lower electrode on a substrate; forming, on the lower electrode, a high dielectric constant film made of an oxide containing a tetravalent metal cation; forming, on the high dielectric constant film, an oxide film made of an oxide containing a pentavalent metal cation; forming a mixed layer having conductivity, in which the oxide containing the tetravalent metal cation and the oxide containing the pentavalent metal cation are mixed, by causing the high dielectric constant film to react with the oxide film; and forming an upper electrode.

2 . The method of claim 1 , wherein the high dielectric constant film made of the oxide containing the tetravalent metal cation is any one of a ZrO 2 film and a HfO 2 film.

3 . The method of claim 1 , wherein the oxide film made of the oxide containing the pentavalent metal cation is any one of a Nb 2 O 5 film, a V 2 O 5 film, and a Ta 2 O 5 film.

4 . The method of claim 1 , wherein the high dielectric constant film made of the oxide containing the tetravalent metal cation is a ZrO 2 film, and the oxide film made of the oxide containing the pentavalent metal cation is a Nb 2 O 5 film.

5 . The method of claim 1 , wherein the upper electrode and the lower electrode are made of a TiN film.

6 . The method of claim 1 , further comprising performing a reduction processing at least after the forming the oxide film.

7 . The method of claim 6 , wherein, in the performing the reduction processing, an oxygen pull-out layer is formed on the mixed layer or the oxide film, and then oxygen is pulled out into the oxygen pull-out layer from the mixed layer or the oxide film by a thermal processing in a reducing atmosphere.

8 . The method of claim 7 , wherein the thermal processing in the reducing atmosphere is performed after the forming the upper electrode.

9 . The method of claim 7 , wherein oxygen deficiency is generated in the mixed layer by pulling out oxygen into the oxygen pull-out layer.

10 . The method of claim 6 , wherein, in the performing the reduction processing, the reduction processing is performed by a thermal processing in a hydrogen gas atmosphere or a deuterium gas atmosphere.

11 . The method of claim 10 , wherein oxygen deficiency is generated in the mixed layer by the thermal processing in the hydrogen gas atmosphere or the deuterium gas atmosphere.

12 . The method of claim 10 , wherein, in the performing the reduction processing, the reduction processing is performed before the forming the upper electrode.

13 . The method of claim 1 , wherein a film thickness of the oxide film is 1 nm or less.

14 . The method of claim 1 , wherein the semiconductor device is a capacitor of a DRAM.

15 . A semiconductor device comprising:
a substrate; a lower electrode formed on the substrate; a high dielectric constant film made of an oxide containing a tetravalent metal cation, and formed on the lower electrode; a mixed layer formed on the high dielectric constant film, the mixed layer having conductivity, in which the oxide containing the tetravalent metal cation and an oxide containing a pentavalent metal cation are mixed; and an upper electrode formed on the mixed layer.

16 . The semiconductor device of claim 15 , wherein the mixed layer has oxygen deficiency.

17 . The semiconductor device of claim 15 , wherein the semiconductor device is used as a capacitor of a DRAM.

Assignees

• Tokyo Electron Ltd

Inventors

• Ikejiri Masahiro
• Akiyama Koji
• Fujiwara Naonori
• Yamazaki Kazuyoshi

Classifications

• H10P14/60

  of insulating materials · CPC title

• H10D1/696

  comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688) · CPC title

• H10B12/00

  Dynamic random access memory [DRAM] devices · CPC title

• H10D1/684 Primary

  the dielectrics comprising multiple layers, e.g. comprising buffer layers, seed layers or gradient layers · CPC title

• H10D1/041

  of capacitors having no potential barriers · CPC title