Semiconductor structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2024387242-A1
Application number	US-202418788276-A
Country	US
Kind code	A1
Filing date	Jul 30, 2024
Priority date	Dec 31, 2015
Publication date	Nov 21, 2024
Grant date	—

Abstract

The present disclosure provides a semiconductor structure, including a first semiconductor device having a first surface and a second surface, the second surface being opposite to the first surface, a semiconductor substrate over the first surface of the first semiconductor device, and a III-V etch stop layer in contact with the second surface of the first semiconductor device. The present disclosure also provides a manufacturing method of a semiconductor structure, including providing a temporary substrate having a first surface, forming a III-V etch stop layer over the first surface, forming a first semiconductor device over the III-V etch stop layer, and removing the temporary substrate by an etching operation and exposing a surface of the III-V etch stop layer.

First claim

1 .- 20 . (canceled)

21 . A manufacturing method of a semiconductor structure, comprising:
providing a first substrate comprising a first material; forming a GaP layer on the first substrate and interfacing the first material; and selectively etching the first substrate to expose a surface of the GaP layer.

22 . The manufacturing method of claim 21 , wherein the first material is silicon.

23 . The manufacturing method of claim 21 , wherein the selectively etching includes performing a basic etch.

24 . The manufacturing method of claim 23 , wherein the performing the basic etch comprises performing a hydrofluoric acid/nitric acid/acetic acid (HNA) etch, a Tetramethylammonium hydroxide (TMAH) etch, or combinations thereof.

25 . The manufacturing method of claim 21 , wherein forming the GaP layer includes forming a thickness of less than 40 nanometers (nm).

26 . The manufacturing method of claim 21 , further comprising:
prior to the selective etching, forming a device layer over the GaP; and forming a semiconductor device in the device layer.

27 . The manufacturing method of claim 26 , wherein the semiconductor device is a photosensing region.

28 . The manufacturing method of claim 26 , wherein the semiconductor device is a transistor.

29 . The manufacturing method of claim 21 , wherein the providing the first substrate provides a P− silicon or P+ silicon substrate.

30 . A method of fabricating a semiconductor device comprising:
providing a substrate comprising:
a first layer comprising P+ silicon and a second layer over the first layer, the second layer comprising P− silicon;
forming an undoped GaP layer over the second layer; and
forming a device layer over the undoped GaP layer; and
forming the semiconductor device on the device layer of the substrate.

31 . The method of claim 30 , wherein a lattice constant of the first layer, the undoped GaP layer and the device layer are substantially the same.

32 . The method of claim 30 , wherein the forming undoped GaP layer and the device layer include epitaxial growth processes.

33 . The method of claim 30 , further comprising:
selectively removing the first layer including:
performing a thinning process of the first layer to form a thinned first layer; and
after the thinning process, performing a wet etch of the thinned first layer, wherein the wet etch includes at least one HF:HNO 3 :CH 3 COOH (HNA) or tetramethylammonium hydroxide (TMAH).

34 . The method of claim 33 , wherein the wet etch includes a first step of wet etching by HNA followed by a second step of wet etching by TMAH, wherein the second step removes the second layer.

35 . A method of fabricating a semiconductor device comprising:
providing a first substrate; forming an undoped GaP layer over the first substrate; growing a first device layer on the undoped GaP layer; forming a semiconductor device on the first device layer; removing a portion of the first substrate by a first removal process; and removing a remaining portion of the first substrate by a second removal process, wherein the second removal process includes a selective etching process exposing the undoped GaP layer.

36 . The method of claim 35 , wherein the second removal process includes HF:HNO 3 :CH 3 COOH (HNA) or tetramethylammonium hydroxide (TMAH).

37 . The method of claim 35 , wherein the removing the portion of the first substrate includes a grinding process.

38 . The method of claim 35 , wherein the first substrate includes a P− silicon layer and a P+ silicon layer.

39 . The method of claim 35 , wherein the undoped GaP layer acts as an insulator.

40 . The method of claim 35 , wherein the forming the undoped GaP layer over the first substrate includes epitaxially growing the undoped GaP layer having a 0.36% lattice mismatch with the first substrate.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tsai Min-Ying
• Tu Yeur-Luen

Classifications

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3218

  Phosphides · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10P50/644

  Anisotropic liquid etching (H10P50/61 takes precedence) · CPC title