Memory devices with integrated fdsoi transistor

Patent metadata

Field	Value
Publication number	US-2024381628-A1
Application number	US-202418659367-A
Country	US
Kind code	A1
Filing date	May 9, 2024
Priority date	May 10, 2023
Publication date	Nov 14, 2024
Grant date	—

Abstract

A variety of applications can include a memory device having a memory array region on a memory die and a periphery to the memory array region on the memory die, where the periphery can include a fully depleted silicon-on-insulator (FDSOI) complementary metal-oxide-semiconductor (CMOS) device. A metal shield can be integrated in the memory array region, where the metal shield is structured as a shield to digit lines of the memory array. A metal body plate in the periphery can be structured as a back gate to the FDSOI CMOS device.

First claim

What is claimed is:

1 . A memory device comprising:
a memory array region on a memory die, the memory array region having an array of memory cells; a periphery to the memory array region on the memory die, the periphery including a fully depleted silicon-on-insulator (FDSOI) complementary metal-oxide-semiconductor (CMOS) device; a metal shield integrated in the memory array region, the metal shield being a shield to digit lines of the array; and a metal body plate arranged as a back gate to the FDSOI CMOS device.

2 . The memory device of claim 1 , wherein the digit lines are metal digit lines.

3 . The memory device of claim 1 , wherein the memory array region includes metal shield lines between adjacent digit lines in the memory array region.

4 . The memory device of claim 3 , wherein the metal shield lines extend vertically from the metal shield in the memory array region.

5 . The memory device of claim 1 , wherein channels of the FDSOI CMOS device are separated from the metal body plate in the periphery by a buried oxide.

6 . The memory device of claim 1 , wherein the metal body plate includes a first body plate separated from a second body plate by an insulating dielectric region.

7 . The memory device of claim 1 , wherein the metal body plate and the metal shield have a common composition.

8 . The memory device of claim 1 , wherein the array of memory cells has a 4F 2 cell configuration.

9 . A method of forming an memory device, the method comprising:
forming metal digit lines of an array of memory cells for the memory device; forming a fully depleted silicon-on-insulator (FDSOI) complementary metal-oxide-semiconductor (CMOS) device in a periphery to the array; and integrating a metal digit shield for the metal digit lines and a metal body plate arranged as a back gate to the FDSOI CMOS device.

10 . The method of claim 9 , wherein the method includes forming the metal digit shield and the metal body plate in backside processing and forming the array in frontside processing.

11 . The method of claim 9 , wherein the method includes forming metal shield lines extending vertically from the metal digit shield between adjacent digit lines.

12 . The method of claim 9 , wherein the method includes forming a sacrificial silicon germanium region to provide an oxide interface for the FDSOI CMOS device.

13 . The method of claim 9 , wherein the method includes forming the array of memory cells having a 4F 2 cell configuration.

14 . The method of claim 9 , wherein the method includes:
forming a chemical mechanical polishing stop on a starting substrate; forming a pillar platform on the chemical mechanical polishing stop; forming a sacrificial silicon-on-insulator region on the pillar platform; forming a silicon-on-insulator platform on the sacrificial silicon-on-insulator region; forming a bonding oxide on the silicon-on-insulator platform; and forming a carrier wafer on the bonding oxide.

15 . The method of claim 14 , wherein the silicon-on-insulator platform has a thickness in a range of about ten to about twenty nanometers.

16 . A method of forming a dynamic random-access memory, the method comprising:
forming a memory array region on a memory die, the memory array region arranged for an array of memory cells having a 4F 2 cell configuration; forming a metal shield integrated in the memory array region, the metal shield being a shield to digit lines of the array; and forming a fully depleted silicon-on-insulator (FDSOI) complementary metal-oxide-semiconductor (CMOS) device in a periphery to the memory array region on the memory die.

17 . The method of claim 16 , wherein the method includes forming metal shield lines extending vertically from the metal shield between adjacent digit lines.

18 . The method of claim 16 , wherein the method includes:
forming a metal body plate in the periphery while forming metal material for the metal shield in the memory array region; and arranging the metal body plate as a back gate to the FDSOI CMOS device.

19 . The method of claim 18 , wherein arranging the metal body plate includes arranging the metal body plate as a first back gate to a first FDSOI transistor and a second back gate to a second FDSOI transistor, the first back gate separated from the second back gate by an insulating region.

20 . The method of claim 16 , wherein the method includes forming a sacrificial silicon germanium region to provide an oxide interface for the FDSOI CMOS device.

Assignees

• Micron Technology Inc

Inventors

• Pulugurtha Srinivas
• Kanago Anthony J

Classifications

• H10B12/315

  with the capacitor higher than a bit line · CPC title

• H10B12/482

  Bit lines · CPC title

• H10B12/50 Primary

  Peripheral circuit region structures · CPC title

• H10B12/09 Primary

  with simultaneous manufacture of the peripheral circuit region and memory cells · CPC title