Floating-Point Dynamic Range Expansion

Patent metadata

Field	Value
Publication number	US-2024345804-A1
Application number	US-202418754921-A
Country	US
Kind code	A1
Filing date	Jun 26, 2024
Priority date	Sep 27, 2018
Publication date	Oct 17, 2024
Grant date	—

Abstract

The present disclosure relates generally to techniques for adjusting the number representation (e.g., format) of a variable before and/or after performing one or more arithmetic operations on the variable. In particular, the present disclosure relates to scaling the range of a variable to a suitable representation based on available hardware (e.g., hard logic) in an integrated circuit device. For example, an input in a first number format (e.g., bfloat16) may be scaled to a second number format (e.g., half-precision floating-point) so that circuitry implemented to receive inputs in the second number format may perform one or more arithmetic operations on the input. Further, the output produced by the circuitry may be scaled back to the first number format. Accordingly, arithmetic operations, such as a dot-product, performed in a first format may be emulated by scaling the inputs to and/or the outputs from arithmetic operations performed in another format.

First claim

What is claimed is:

1 . An integrated circuit, comprising:
conversion circuitry configurable to:
receive a set of inputs having a first number format; and
generate a set of converted inputs by converting the set of inputs from the first number format to a second number format, wherein the second number format comprises an exponent value less than an exponent value of the first number format; and
arithmetic circuitry communicatively coupled to the conversion circuitry and configurable to perform an arithmetic operation on the set of converted inputs to produce an output.

2 . The integrated circuit of claim 1 , wherein the arithmetic operation comprises a multiply and an accumulate.

3 . The integrated circuit of claim 2 , wherein the arithmetic circuitry is configurable produce the output in a third number format greater than the first number format.

4 . The integrated circuit of claim 3 , comprising post-conversion circuitry configurable to receive the output from the arithmetic circuitry and convert the output from the third number format to the first number format.

5 . The integrated circuit of claim 4 , wherein the conversion circuitry is configurable to scale the set of inputs based on a scaling factor.

6 . The integrated circuit of claim 5 , wherein the conversion circuitry is configurable to determine the scaling factor based on a maximum value of the set of inputs.

7 . The integrated circuit of claim 6 , comprising a memory configurable to store the maximum value.

8 . The integrated circuit of claim 1 , wherein the second number format comprises a 4-bit exponent or a 5-bit exponent.

9 . The integrated circuit of claim 1 , wherein the conversion circuitry is configurable to convert between the first number format and the second number format by adjusting the exponent value of the first number format from a first number of bits to a second number of bits.

10 . The integrated circuit of claim 1 , wherein the first number format comprises a half-precision floating-point number.

11 . A method, comprising:
receiving, via processing circuitry, a set of inputs having a first number format; generating, via the processing circuitry, a set of converted inputs by converting the set of inputs from the first number format to a second number format, wherein the second number format comprises an exponent value less than the exponent value of the first number format; determining, via the processing circuitry, a scaling factor based on a maximum value of the set of converted inputs; generating, via the processing circuitry, a set of scaled converted inputs by scaling the set of converted input by the scaling factor; and generating, via the processing circuitry, an output by performing an arithmetic operation on the set of scaled converted inputs, wherein the output is in a third number format greater than the first number format.

12 . The method of claim 11 , comprising converting, via the processing circuitry, the output from the third number format back to the first number format.

13 . The method of claim 11 , wherein generating, via the processing circuitry, the set of scaled input comprises converting the exponent value of the first number format from a first number of bits to a second number of bits.

14 . The method of claim 11 , comprising determining, via the processing circuitry, a target number format prior to generating the set of scaled inputs, wherein the target number format is the second number format.

15 . The method of claim 11 , wherein the arithmetic operation comprises a multiply and an accumulate.

16 . A system, comprising:
a substrate; a processor mounted on the substrate; a memory mounted on the substrate; and an integrated circuit device mounted on the substrate and communicatively coupled to the processor and the memory, wherein the integrated circuit device comprises:
conversion circuitry configurable to:
receive a set of inputs having a first range; and
convert the set of inputs from a first number format to a second number format; and
scale the set of inputs based on a scaling factor to generate a set of scaled inputs; and

arithmetic circuitry communicatively coupled to the conversion circuitry and configurable to perform one or more arithmetic operations on the set of scaled inputs to generate an output, wherein the output is in a third number format greater than the first number format.

17 . The system of claim 16 , wherein the conversion circuitry is configurable to determine the scaling factor based on a maximum value of the set of inputs.

18 . The system of claim 16 , wherein the conversion circuitry is configurable to convert the set of inputs from the first number format to the second number format by converting the respective exponent of each input of the set of inputs from a first number of bits to a second number of bits.

19 . The system of claim 16 , wherein the one or more arithmetic operations comprises a multiply and an accumulate.

20 . The system of claim 16 , wherein the output comprises 16-bits or 32-bits.

Assignees

• Intel Corp

Inventors

• Pasca Bogdan Mihai
• Langhammer Martin

Classifications

• G06F7/575

  Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry · CPC title

• G06F7/5443

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title

• G06F7/4876 Primary

  Multiplying · CPC title