Data processing apparatus and method for multiplying floating point operands

Patent metadata

Field	Value
Publication number	US-9483232-B2
Application number	US-201414200923-A
Country	US
Kind code	B2
Filing date	Mar 7, 2014
Priority date	Mar 7, 2014
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

A data processing apparatus and method are provided for multiplying first and second normalized floating point operands in order to generate a result, each normalized floating point operand comprising a significand and an exponent. Exponent determination circuitry is used to compute a result exponent for a normalized version of the result, and rounding value generation circuitry then generates a rounding value by shifting a rounding constant in a first direction by a shift amount that is dependent on the result exponent. Partial product generation circuitry multiplies the significands of the first and second normalized floating point operands to generate the first and second partial products, and the first and second partial products are then added together, along with the rounding value, in order to generate a normalized result significand. Thereafter, the normalized result significand is shifted in a second direction opposite to the first direction, by the shift amount, in order to generate a rounded result significand. This provides a particularly efficient mechanism for multiplying floating point numbers, while correctly rounding the result in situations where the result is subnormal.

First claim

We claim:

1. A data processing apparatus for multiplying first and second normalized floating point operands to generate a result, each normalized floating point operand comprising a significand and an exponent, the data processing apparatus comprising:
exponent determination circuitry configured to compute a result exponent for a normalized version of the result;
rounding value generation circuitry configured to generate a rounding value by shifting a rounding constant in a first direction by a shift amount that is dependent on the result exponent;
partial product generation circuitry configured to multiply the significands of the first and second normalized floating point operands to generate first and second partial products;
adder circuitry configured to add the first and second partial products and the rounding value to generate a normalized result significand; and
shifting circuitry configured to shift the normalized result significand in a second direction opposite to said first direction, by said shift amount in order to generate a rounded result significand.

2. A data processing apparatus as claimed in claim 1 , further comprising:
mask generation circuitry configured to generate a mask value by shifting a mask constant in said first direction by said shift amount;
guard and sticky bit detection circuitry configured to apply the mask value to the normalized result significand to identify guard and sticky bits within the normalized result significand; and
result adjustment circuitry configured to adjust the rounded result significand dependent on the guard and sticky bits.

3. A data processing apparatus as claimed in claim 2 , wherein each bit of the mask constant is set to a predetermined bit value, and the mask generation circuitry is configured, when shifting the mask constant in said first direction by said shift amount, to set to said predetermined bit value the least significant bit positions from which the mask constant is shifted and to include those least significant bit positions in the mask value along with the shifted mask constant.

4. A data processing apparatus as claimed in claim 1 , wherein said shift amount is set to identify a zero shift if the result exponent is in a normal range.

5. A data processing apparatus as claimed in claim 1 , further comprising an input interface for receiving first and second input floating point operands used to form said first and second normalized floating point operands, the data processing apparatus comprising:
normalization circuitry configured to be responsive to one of said first and second input floating point operands being a subnormal operand, to form the corresponding normalized floating point operand to have a significand formed by shifting the significand of the subnormal operand in said first direction by a normalising amount and to have an exponent formed by adjusting the exponent of the subnormal operand dependent on said normalising amount.

6. A data processing apparatus as claimed in claim 1 , further comprising:
shift amount generation circuitry configured to generate said shift amount such that, if the result exponent is subnormal, the shift amount is dependent on a difference between the result exponent and a minimum normal exponent value.

7. A data processing apparatus as claimed in claim 6 , wherein the shift amount generation circuitry is configured to restrict the shift amount to not exceed a predetermined maximum shift amount.

8. A data processing apparatus as claimed in claim 1 , wherein the rounding constant is dependent on a rounding mode used by the data processing apparatus.

9. A data processing apparatus as claimed in claim 1 , wherein the rounding value generation circuitry is configured, when shifting the rounding constant in said first direction by said shift amount, to set to a predetermined bit value the least significant bit positions from which the rounding constant is shifted, and to include those least significant bit positions in the rounding value along with the shifted rounding constant.

10. A data processing apparatus as claimed in claim 9 , wherein the predetermined bit value is dependent on a rounding mode used by the data processing apparatus.

11. A method of operating a data processing apparatus to multiply first and second normalized floating point operands in order to generate a result, each normalized floating point operand comprising a significand and an exponent, the method comprising:
computing, by exponent determination circuitry, a result exponent for a normalized version of the result;
generating, by rounding value generation circuitry, a rounding value by shifting a rounding constant in a first direction by a shift amount that is dependent on the result exponent;
multiplying, by partial product generation circuitry, the significands of the first and second normalized floating point operands to generate first and second partial products;
adding, by adding circuitry, the first and second partial products and the rounding value to generate a normalized result significand; and
shifting, by shifting circuitry, the normalized result significand in a second direction opposite to said first direction, by said shift amount in order to generate a rounded result significand.

12. A data processing apparatus for multiplying first and second normalized floating point operands to generate a result, each normalized floating point operand comprising a significand and an exponent, the data processing apparatus comprising:
means for computing a result exponent for a normalized version of the result;
means for generating a rounding value by shifting a rounding constant in a first direction by a shift amount that is dependent on the result exponent;
means for multiplying the significands of the first and second normalized floating point operands to generate first and second partial products;
means for adding the first and second partial products and the rounding value to generate a normalized result significand; and
means for shifting the normalized result significand in a second direction opposite to said first direction, by said shift amount in order to generate a rounded result significand.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Lutz David Raymond
• Burgess Neil

Classifications

• G06F2207/483

  Indexing scheme relating to group G06F7/483 · CPC title

• G06F7/49952

  Sticky bit · CPC title

• G06F7/5336

  overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm · CPC title

• G06F5/012

  in floating-point computations · CPC title

• G06F7/4876 Primary

  Multiplying · CPC title