Computation of correctly rounded floating point summation
US-2024160405-A1 · May 16, 2024 · US
Multiplying
Multiplying · Cooperative Patent Classification (CPC)
Computing, optics, measurement, and control technologies.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | G06F7/4876 |
| Official title | {Multiplying} |
| Display label | Multiplying |
| Total patents | 640 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is stable.
| Year | Patents |
|---|---|
| 2015 | 11 |
| 2016 | 21 |
| 2017 | 31 |
| 2018 | 37 |
| 2019 | 50 |
| 2020 | 55 |
| 2021 | 66 |
| 2022 | 100 |
| 2023 | 83 |
| 2024 | 102 |
| 2025 | 71 |
| 2026 | 13 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Processor with Backside Look-Up Table
US-2017322770-A1 · Nov 9, 2017 · US
Simulation Processor with Backside Look-Up Table
US-2017323042-A1 · Nov 9, 2017 · US
Standard format intermediate result
US-9798519-B2 · Oct 24, 2017 · US
Reducing power consumption in a fused multiply-add (FMA) unit of a processor
US-9778911-B2 · Oct 3, 2017 · US
Temporally split fused multiply-accumulate operation
US-9778908-B2 · Oct 3, 2017 · US
Double rounded combined floating-point multiply and add
US-9778909-B2 · Oct 3, 2017 · US
Non-atomic split-path fused multiply-accumulate
US-9778907-B2 · Oct 3, 2017 · US
Unified Multiply Unit
US-2017277514-A1 · Sep 28, 2017 · US
Processor Comprising Three-Dimensional Memory (3D-M) Array
US-2017237440-A1 · Aug 17, 2017 · US
Stochastic rounding floating-point multiply instruction using entropy from a register
US-2017220343-A1 · Aug 3, 2017 · US
Stochastic rounding floating-point multiply instruction using entropy from a register
US-2017220341-A1 · Aug 3, 2017 · US
Binary fused multiply-add floating-point calculations
US-2017220319-A1 · Aug 3, 2017 · US
Binary fused multiply-add floating-point calculations
US-2017220318-A1 · Aug 3, 2017 · US
Optimized structure for hexadecimal and binary multiplier array
US-9720648-B2 · Aug 1, 2017 · US
Highly integrated scalable, flexible dsp megamodule architecture
US-2017153890-A1 · Jun 1, 2017 · US
Floating point multiply accumulator multi-precision mantissa aligner
US-2017147288-A1 · May 25, 2017 · US
Two address translations from a single table look-asside buffer read
US-2017132149-A1 · May 11, 2017 · US
Method and device for checking a digital multiplier
US-9612796-B2 · Apr 4, 2017 · US
Apparatus and method for floating-point multiplication
US-2017090869-A1 · Mar 30, 2017 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC G06F7/4876?
- CPC G06F7/4876 is the Cooperative Patent Classification code for “Multiplying.”
- How many patents are filed under CPC G06F7/4876 (Multiplying)?
- Our database includes 640 publications tagged with this CPC code.
- Is patent activity under CPC G06F7/4876 growing?
- Publication counts under this code: 102 in 2024 vs 71 in 2025 (latest complete years).