System and method for thread scheduling on reconfigurable processor cores

Patent metadata

Field	Value
Publication number	US-9703708-B2
Application number	US-201314040142-A
Country	US
Kind code	B2
Filing date	Sep 27, 2013
Priority date	Sep 27, 2013
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

Systems and methods for efficiently utilizing reconfigurable processor cores. An example processing system includes, for example, a control register comprising a plurality of inhibit bits, each inhibit bit indicating whether a corresponding processor core is allowed to merge with other processor cores; and dynamic core reallocation logic to temporarily merge a first processor core and a second processor core to speed execution of a first thread executed on the first processor core responsive to determining that a second thread executed on the second processor core has completed execution prior to a quantum associated with the second thread being reached and to determining that the inhibit bits indicate that the first and second cores may be merged.

First claim

We claim:

1. A processing system, comprising:
a plurality of processor cores, including a first processor core executing a first thread and a second processor core executing a second thread;
a control register comprising a plurality of inhibit bits associated with a respective processor core and a plurality of state bits associated with a respective processor core, each inhibit bit indicating whether the corresponding processor core is inhibited to merge with another processor core, and each state bit indicating whether the corresponding processor core is currently executing its respective thread; and
dynamic core reallocation logic automatically performing:
in response to a trap of the execution of the second thread indicating its completion in execution prior to a quantum associated with all threads of the system being reached, clearing the state bit of the second processor core,
periodically checking for cleared state bits of the control register;
upon determining a cleared state bit, estimating that the first thread executing on the first processing core having a state bit set, would have the most benefit in its execution with additional resources among other processing cores having their respective state bits set;
determining if the inhibit bits of the first and second processor cores are set or not;
if the inhibit bits of the first and second processor cores are not set, temporarily merging a first processor core and a second processor core to speed up execution of a first thread currently being executed on the first processor core;
if either the inhibit bits of the first or second processor core are set, avoid merging a first processor core and a second processor core to speed up execution of the first thread currently being executed on the first processor core;
determining if the quantum period associated with the first and second threads has been reached;
in response to determining that the quantum of the first and second threads has been reached, executing morphing cleanup which deallocates the second processor core from the merged processor cores, and allocating a new thread to the second processor core for execution.

2. The processing system of claim 1 wherein the dynamic core reallocation logic temporarily stores a state associated with the second thread in some state memory storage while the first and second processor cores are merged.

3. The processing system of claim 2 wherein the dynamic core reallocation logic restores the state associated with the second thread responsive to the quantum of the second thread being reached.

4. The processing system of claim 2 , wherein the dynamic core reallocation logic is further configured, responsive to determining that the second processor core is to transition into active, to restore the state of the second processor core from the state memory storage and re-partition the first processor core and the second processor core.

5. The processing system of claim 2 , wherein the state memory storage resides in one of: an on-die cache, an on-die memory, an off-die cache, an off-die memory.

6. The processing system of claim 5 wherein the state memory storage resides in an LI cache and/or an L2 cache.

7. The processing system of claim 1 , wherein the control register is writable by a thread executing by the processing system at a privileged level of execution.

8. The processing system of claim 1 , wherein at least one processor core comprises an out-of-order core or an in-order core.

9. The processing system of claim 1 , wherein each processor core comprises a core or a context within a core.

10. A method, comprising:
executing a first thread on a first processor core and a second thread on a second processor core on a multi-core processor, wherein the multi-core processor further comprising a control register comprising a plurality of inhibit bits associated with a respective processor core of the multi-core processor and a plurality of state bits associated with a respective processor core of the multi-core processor, each inhibit bit indicating whether the corresponding processor core is inhibited to merge with another processor core, and each state bit indicating whether the corresponding processor core is currently executing its respective thread; and
in response to a trap of the execution of the second thread indicating its completion in execution prior to a quantum associated with all threads of the system being reached, automatically clearing, by a dynamic core reallocation logic, the state bit of the second processor core, and
periodically checking, by the dynamic core reallocation logic, for cleared state bits of the control register;
upon determining a cleared state bit, estimating, by the dynamic core reallocation logic, that the first thread executing on the first processing core having a state bit set, would have the most benefit in its execution with additional resources among other processing cores having their respective state bits set;
determining, by the dynamic core reallocation logic, if the inhibit bits of the first and second processor cores are set or not;
if the inhibit bits of the first and second processor cores are not set, temporarily merging, by the dynamic core reallocation logic, a first processor core and a second processor core to speed up execution of the first thread currently being executed on the first processor core;
if either the inhibit bits of the first or second processor core are set, avoid merging, by the dynamic core reallocation logic, a first processor core and a second processor core to speed up execution of the first thread currently being executed on the first processor core;
determining, by the dynamic core reallocation logic, if the quantum period associated with the first and second threads has been reached;
in response to determining that the quantum of the first and second threads has been reached, executing, by the dynamic core reallocation logic, morphing cleanup which deallocates the second processor core from the merged processor cores, and
allocating, by the dynamic core reallocation logic, a new thread to the second processor core for execution.

11. The method as in claim 10 further comprising:
storing a state of the first processor core in a memory prior to merging the first processor core with the second processor core.

12. The method of claim 11 further comprising:
restoring the state associated with the first thread responsive to the first quantum of the first thread being reached.

13. The method of claim 11 wherein the memory resides in one of: an on-die cache, an on-die memory, an off-die cache, an off-die memory.

14. The method of claim 13 wherein the memory resides in an LI cache and/or an L2 cache.

15. The method of claim 10 , wherein the control register is writable by a thread executing by a processing system at a privileged level of execution.

16. The method of claim 10 , wherein at least one processor core comprises an out-of-order core or an in-order core.

17. The method of claim 10 , wherein at least one processor core comprises an in-order core.

18. A non-transitory machine-readable medium having program code stored thereon which, when executed by a multi-core processor, causes the multi-core processor to perform operations of:
executing a first thread on a first processor core and a second thread on a second processor core on the multi-core processor, wherein the multi-core processor further comprising a control register comprising a plurality of inhibit bits associated with a respective processor core of

Assignees

• Intel Corp

Inventors

• Alameldeen Alaa R
• Wilkerson Christopher B
• Gorbatov Eugene
• Chishti Zeshan A

Classifications

• G06F9/5061

  Partitioning or combining of resources · CPC title

• Y02B60/1225

  Cross-Sectional Technologies · mapped topic

• Y02B60/142

  Cross-Sectional Technologies · mapped topic

• Y02B60/167

  Cross-Sectional Technologies · mapped topic

• G06F2209/5012

  Processor sets · CPC title