High-throughput silicon carbide reactor

Patent metadata

Field	Value
Publication number	US-2024175130-A1
Application number	US-202318523021-A
Country	US
Kind code	A1
Filing date	Nov 29, 2023
Priority date	Nov 30, 2022
Publication date	May 30, 2024
Grant date	—

Abstract

Methods and systems for growing silicon carbide epitaxial layers are described. In one example, a reactor system with multiple reactor modules may include a heating load/lock chamber and a cooling load/lock chamber. In another example, a reactor may be heated by separate sets of coils inductively heating a susceptor, which heats graphite near one or more wafers. Multiple pyrometers may measure the temperature of the graphite walls at different locations. Based on temperature differences and/or temperature gradients, a temperature controller may adjust power provided to one or more sets of coils. In yet another example, separations between a wafer carrier and a wafer may be adjusted.

First claim

What is claimed is:

1 . A system comprising:
a plurality of reactor modules configured to perform semiconductor processes on wafers; a plurality of loading/unloading stations; one or more load/lock chambers configured to modify a temperature of the wafers; a substrate handling chamber comprising a first substrate transfer assembly, wherein the first substrate transfer assembly is configured to transfer the wafers between the plurality of reactor modules and the one or more load/lock chambers; and a transfer chamber comprising a second substrate transfer assembly, wherein the second substrate transfer assembly is configured to transfer the wafers between the plurality of loading/unloading stations and the one or more load/lock chambers.

2 . The system of claim 1 , wherein the first substrate transfer assembly is configured to transfer the wafers individually between the reactor modules and the one or more load/lock chambers.

3 . The system of claim 1 , wherein the first substrate transfer assembly is configured to transfer the wafers on a wafer carrier between the reactor modules and the one or more load/lock chambers.

4 . The system of claim 1 , wherein the one or more load/lock chambers are configured to both heat and cool wafers.

5 . The system of claim 1 , wherein the one or more load/lock chambers comprise:
a heating load/lock chamber configured to heat wafers; and a cooling load/lock chamber configured to cool wafers.

6 . A method comprising:
receiving, at a loading station, a plurality of wafers at a first temperature; transferring, via a first substrate transfer assembly, the plurality of wafers to a load/lock station; heating, from the first temperature to a second temperature, the wafers in the load/lock station; transferring, via a second substrate transfer assembly, the wafers from the load/lock station to a first reactor module, wherein the first reactor module comprises a first reaction chamber; heating, in the first reactor module and from the second temperature to a third temperature, the wafers; performing a first semiconductor production process on the wafers; transferring, via the second substrate transfer assembly, the wafers to the load/lock station; cooling, to a temperature lower than the third temperature, the wafers; and transferring, via the first substrate transfer assembly, the plurality of wafers to the loading station.

7 . The method of claim 6 ,
wherein the load/lock station comprises a heating load/lock station and a cooling load/lock station, wherein the heating is performed in the heating load/lock station, and wherein transferring the wafers from the load/lock station to the first reactor module comprises:
transferring the wafers from the heating load/lock station to the first reactor module.

8 . The method of claim 7 , wherein transferring the wafers from the first reactor module to the load/lock station comprises:
transferring the wafers from the first reactor module to the cooling load/lock station.

9 . The method of claim 6 ,
wherein the lower temperature is a temperature at which the wafers are unloaded, and wherein the second temperature is higher than the lower temperature.

10 . The method of claim 6 , further comprising:
transferring, after performing the first process on the wafers and via the second substrate transfer assembly, the wafers from the first reactor module to a second reactor module; heating, in second reactor module and to a fourth temperature, the wafers; and performing a second process on the wafers, wherein transferring the wafers to the load/lock station further comprises transferring the wafers from the second reactor module to the load/lock station.

11 . The method of claim 6 ,
wherein the first temperature is room temperature, wherein the second temperature is approximately 400° C.±50° C., and wherein the third temperature is at or above 1200° C.

12 . The method of claim 6 , wherein performing the first process on the wafers comprises:
etching the wafers; conditioning the first reaction chamber; heating the wafers to a fourth temperature; and epitaxially growing silicon carbide on the wafers.

13 . The method of claim 12 ,
wherein the fourth temperature is at or above 1750° C.

14 . A system comprising:
a reactor chamber comprising outer walls and inner walls; a wafer carrier configured to support one or more wafers; a spindle configured to rotate the wafer carrier; graphite walls above and below the wafer carrier, wherein the inner walls and the graphite walls define a gas flow path; a susceptor above and below the graphite walls; two or more coils configured to inductively heat the susceptor; a power supply configured to energize the coils; two or more pyrometers configured to measure temperatures of the graphite wall; and a temperature controller configured to control, based on the temperatures and via the power supply, power supplied to at least one of the coils.

15 . The system of claim 14 , wherein the susceptor comprises a ceramic material.

16 . The system of claim 14 , wherein the temperature controller is configured to control the power supplied to the at least one of the coils based on a temperature differential between the two or more pyrometers.

17 . The system of claim 14 ,
wherein the two or more pyrometers comprise three or more pyrometers configured to measure temperatures of the graphite walls; and wherein the temperature controller is configured to control the power supplied to the at least one of the coils based on a temperature gradient of the graphite walls.

18 . The system of claim 14 ,
wherein the two or more pyrometers are spaced in a radial direction outward from an axis of the spindle.

19 . A method comprising:
powering two or more sets of coils to inductively heat a susceptor; receiving, from two or more pyrometers, signals relating to temperatures of graphite walls, wherein the graphite walls are heated by the susceptor; determining, based on the signals, a temperature differential; determining whether the temperature differential satisfies a threshold; and controlling, based on a determination that the temperature differential satisfies the threshold, power supplied to at least one set of the two or more sets of coils.

20 . The method of claim 19 , wherein receiving signals further comprises:
receiving, from three or more pyrometers, signals relating to temperatures of the graphite walls, wherein determining the temperature differential comprises determining a temperature gradient across the graphite walls, and wherein determining whether the temperature differential satisfies a threshold comprises determining whether the temperature gradient satisfies a temperature gradient threshold.

21 . A method comprising:
selecting a first wafer carrier comprising a first wafer support surface, configured to support a wafer, and a first horizontal lip surface parallel to and elevated, by a first vertical distance, from the first wafer support surface; growing, in a reactor and on an upper surface of the wafer, an epitaxial layer, wherein the wafer is supported, in the reactor, by the first wafer support surface of the first wafer carrier, wherein the first wafer carrier is rotated in the reactor about a center of rotation; determining, from a circumferential edge and in a radial direction of the first wafer carrier, thicknesses of the epitaxial layer at two or more locations of

Assignees

• Asm Ip Holding Bv

Inventors

• M’Saad Hichem
• Raaijmakers Ivo Johannes
• Lin Xing
• Wang Wentao
• Terhorst Herbert

Classifications

• H10P72/3302

  Mechanical parts of transfer devices · CPC title

• H10P72/0602 Primary

  Temperature monitoring · CPC title

• H10P72/0466

  characterised by the construction of the load-lock chamber · CPC title

• H10P72/0431

  Apparatus for thermal treatment · CPC title

• H10P72/7621

  characterised by supporting two or more semiconductor substrates · CPC title