High retention time memory element with dual gate devices

Patent metadata

Field	Value
Publication number	US-2020066326-A1
Application number	US-201515776058-A
Country	US
Kind code	A1
Filing date	Dec 23, 2015
Priority date	Dec 23, 2015
Publication date	Feb 27, 2020
Grant date	—

Abstract

A high retention time memory element is described that has dual gate devices. In one example, the memory element has a write transistor with a metal gate having a source coupled to a write bit line, a gate coupled to a write line, and a drain coupled to a storage node, wherein a value is written to the storage node by enabling the gate and applying the value to the bit line, and a read transistor having a source coupled to a read line, a gate coupled to the storage node, and a drain coupled to a read bit line, wherein the value of the storage node is sensed by applying a current to the source and reading the sense line to determine a status of the gate.

First claim

1 . A memory element comprising:
a write transistor with a low off state gate leakage having a source coupled to a write bit line, a gate coupled to a write line, and a drain coupled to a storage node, wherein a value is written to the storage node by enabling the gate and applying the value to the bit line; and a read transistor having a source coupled to a read line, a gate coupled to the storage node, and a drain coupled to a read bit line, wherein the value of the storage node is sensed by applying a current to the source and reading the sense line to determine a status of the gate.

2 . The memory element of claim 1 , wherein the write transistor has a gate threshold voltage that is higher than the bit line voltage.

3 . The memory element of claim 1 , wherein the write transistor has a metal gate.

4 . memory element of claim 1 , wherein the write transistor is a thick gate transistor.

5 . The memory element of claim 1 , wherein the write transistor has an Indium Gallium Zinc Oxide structure.

6 . The memory element of claim 1 , wherein the read transistor has a low gate leakage.

7 . The memory element of claim 1 , wherein the read transistor has a metal gate.

8 . The memory element of claim 1 , wherein the read transistor has an Indium Gallium Zinc Oxide structure.

9 . The memory element of claim 1 , wherein the write and read transistors are stacked one over the other.

10 . The memory element of claim 9 , wherein the write transistor is over a write bit line, the storage node is stacked over the write transistor and the read transistor is stacked over the storage node.

11 . The memory element of claim 9 , wherein the write and read transistors are formed in metal layers of an integrated circuit die.

12 . The memory element of claim 11 , wherein the write bit line, write line, read line, and read bit line are coupled to logic circuits of the die through vertical vias through the metal layers.

13 . The memory element of claim 1 , further comprising a plurality of additional write transistors and wherein the write bit line and write line are coupled to the plurality of additional transistors.

14 . The memory element of claim 1 , further comprising a third transistor between the write transistor and the read transistor, the third transistor having a gate coupled to the drain of the write transistor and a drain coupled to the source of the read transistor.

15 . A method comprising:
forming a word write line as a horizontal layer in a first metal layer of an integrated circuit die; forming a first metal gate thin film transistor over the write line so that the word write line is coupled to the first transistor gate; forming a write bit line in a second metal layer over the first transistor so that the write bit line is coupled to the first transistor source; forming a storage node in the second metal layer over the first transistor so that the storage node is coupled to the first transistor drain; forming second transistor over the storage node so that a gate of the second transistor is coupled to the storage node; forming a read bit line in a third metal layer over the second transistor so that the read bit line is coupled to a drain of the second transistor; and forming a read line in the third metal layer over the second transistor so that the read line is coupled to a source of the transistor.

16 . The method of claim 15 , wherein forming a first transistor comprises forming an Indium Gallium Zinc Oxide transistor.

17 . The method of claim 15 , further comprising forming a vertical via from the read bit line to active circuitry of the integrated circuit die below the first transistor.

18 . A computing system comprising:
a system board; a memory connected to the system board; and a processor coupled to the memory through the system board, the processor being formed of active circuitry on a substrate and having a plurality of metal layers over the active circuitry, the metal layers including a memory array having a plurality of memory elements each memory element including a write transistor with a low off state gate leakage having a source coupled to a write bit line, a gate coupled to a write line, and a drain coupled to a storage node, wherein a value is written to the storage node by enabling the gate and applying the value to the write bit line, and a read transistor having a source coupled to a read line, a gate coupled to the storage node, and a drain coupled to a read bit line, wherein the value of the storage node is sensed by applying a current to the source and reading the read bit line to determine a status of the gate.

19 . The computing system of claim 18 , wherein the write bit line, write line, read line, and read bit line are coupled to logic circuits of the die through vertical vias through the metal layers.

20 . The computing system of claim 18 , wherein the write bit line, write line, read line, and read bit line are shared among memory elements of memory array.

Assignees

• Intel Corp

Inventors

• Rios Rafael
• Dewey Gilbert
• Le Van H
• Kavalieros Jack
• Meterelliyoz Mesut

Classifications

• G11C11/405

  with three charge-transfer gates, e.g. MOS transistors, per cell · CPC title

• G11C2211/4068

  Voltage or leakage in refresh operations · CPC title

• G11C11/4097 Primary

  Bit-line organisation, e.g. bit-line layout, folded bit lines · CPC title

• G11C11/409 Primary

  Read-write [R-W] circuits · CPC title

• G11C11/404

  with one charge-transfer gate, e.g. MOS transistor, per cell · CPC title