One transistor and one ferroelectric capacitor memory cells in diagonal arrangements

Patent metadata

Field	Value
Publication number	US-2020091162-A1
Application number	US-201816132281-A
Country	US
Kind code	A1
Filing date	Sep 14, 2018
Priority date	Sep 14, 2018
Publication date	Mar 19, 2020
Grant date	—

Abstract

Described herein are one access transistor and one ferroelectric capacitor (1T-1FE-CAP) memory cells in diagonal arrangements, as well as corresponding methods and devices. When access transistors of memory cells are implemented as FinFETs, then, in a first diagonal arrangement, memory cells are arranged so that the BLs for the cells are diagonal with respect to the fins of the access transistors of the cells, while the WLs for the cells are perpendicular to the fins. In a second diagonal arrangement, memory cells are arranged so that the fins of the access transistors of the cells are diagonal with respect to the WLs for the cells, while the BLs for the cells are perpendicular to the WLs. Such diagonal arrangements may advantageously allow achieving high layout densities of 1T-1FE-CAP memory cells and may benefit from the re-use of front-end transistor process technology with relatively minor adaptations.

First claim

1 . A memory device, comprising:
a transistor; and a ferroelectric capacitor comprising a first capacitor electrode, a second capacitor electrode, and a ferroelectric material between the first and second capacitor electrodes, wherein:
the transistor includes a fin of a semiconductor material, the fin extending away from a base,
the transistor includes a first source/drain (S/D) terminal coupled to a bitline (BL),
the transistor includes a second S/D terminal coupled to the second capacitor electrode, and
a projection of the BL on a plane parallel to the base is at an angle between 5 and 45 degrees with respect to a projection of the fin on the plane.

2 . The memory device according to claim 1 , wherein the projection of the BL on the plane is at an angle between 10 and 30 degrees with respect to the projection of the fin on the plane.

3 . The memory device according to claim 1 , further comprising at least a first interconnect layer and a second interconnect layer above the base, wherein the first interconnect layer is between the base and the second interconnect layer, and wherein the BL is in the first interconnect layer.

4 . The memory device according to claim 3 , wherein the second capacitor electrode is in the second interconnect layer or in a third interconnect layer that is farther away from the base than the second interconnect layer.

5 . The memory device according to claim 3 , further comprising one or more conductive vias extending through at least the first interconnect layer to couple the second capacitor electrode to the second S/D terminal of the transistor.

6 . The memory device according to claim 1 , wherein the BL has a first face and an opposing second face, the first face is closer to the base than the second face, and the memory device further includes an etch stop material over at least a portion of the second face of the BL.

7 . The memory device according to claim 6 , wherein the memory device further includes the etch stop material over at least a portion of at least one sidewall of the BL, and the sidewall extends between the second face and the first face.

8 . The memory device according to claim 6 , wherein the memory device further includes a BL contact coupling the BL and the first S/D terminal of the transistor, and wherein the etch stop material at least partially wraps around the BL and the BL contact.

9 . The memory device according to claim 1 , wherein the transistor further includes a gate terminal coupled to a wordline (WL), and wherein the projection of the fin on the plane parallel to the base is perpendicular to the projection of the WL on the plane.

10 . The memory device according to claim 1 , wherein the first S/D terminal is a source terminal.

11 . A memory device, comprising:
a transistor; and a ferroelectric capacitor comprising a first capacitor electrode, a second capacitor electrode, and a ferroelectric material between the first and second capacitor electrodes, wherein:
the transistor includes a fin of a semiconductor material, the fin extending away from a base,
the transistor is coupled to the ferroelectric capacitor,
a gate terminal of the transistor is coupled to a wordline (WL), and
a projection of the WL on a plane parallel to the base is at an angle between 5 and 45 degrees with respect to a projection of the fin on the plane.

12 . The memory device according to claim 11 , wherein the projection of the WL on the plane is at an angle between 10 and 30 degrees with respect to the projection of the fin on the plane.

13 . The memory device according to claim 11 , wherein:
the transistor further includes a first source/drain (S/D) terminal and a second S/D terminal, the transistor is coupled to the ferroelectric capacitor by having the second S/D terminal of the transistor being coupled to the second capacitor electrode, and the first S/D terminal of the transistor is coupled to a bitline (BL).

14 . The memory device according to claim 13 , wherein a projection of the BL on the plane is perpendicular to the projection of the WL on the plane.

15 . The memory device according to claim 11 , wherein the ferroelectric material comprises one or more of:
a ferroelectric material comprising hafnium, zirconium, and oxygen; a ferroelectric material comprising hafnium, silicon, and oxygen; a ferroelectric material comprising hafnium, germanium, and oxygen; a ferroelectric material comprising hafnium, aluminum, and oxygen; or a ferroelectric material comprising hafnium, yttrium, and oxygen.

16 . The memory device according to claim 11 , wherein the ferroelectric material has a thickness between 1 nanometer and 10 nanometers.

17 . The memory device according to claim 11 , wherein the first capacitor electrode is coupled to a plateline.

18 . A method of operating a memory device comprising an access transistor and a ferroelectric capacitor, the method comprising:
driving a wordline (WL), coupled to a gate terminal of the access transistor, to cause the access transistor to turn on; and programming the ferroelectric capacitor by, when the access transistor is turned on, driving a bitline (BL) coupled to a first source/drain (S/D) terminal of the access transistor to charge or discharge an intermediate node coupled to a second S/D terminal of the access transistor, wherein the ferroelectric capacitor is coupled to and programmable according to a charge on the intermediate node, wherein the access transistor includes a fin of a semiconductor material, and wherein:
either a projection of the BL on a plane parallel to a substrate over which the memory device is provided is at an angle between 5 and 45 degrees with respect to a projection of the fin on the plane,
or a projection of the WL on said plane is at an angle between 5 and 45 degrees with respect to the projection of the fin on the plane.

19 . The method according to claim 18 , wherein a first capacitor electrode of the ferroelectric capacitor is coupled to a plateline (PL), a second capacitor electrode of the ferroelectric capacitor is coupled to the intermediate node, and the ferroelectric material is between the first capacitor electrode and the second capacitor electrode.

20 . The method according to claim 19 , wherein programming the ferroelectric capacitor includes applying a first voltage to the PL to generate an electric field across the ferroelectric material, and wherein driving the WL and driving the BL are performed after applying the first voltage to the PL.

21 . The method according to claim 20 , wherein application of the first voltage to the PL causes a first logic state to be programmed on the ferroelectric capacitor, the method further comprising applying a second voltage to the PL after applying the first voltage to the PL, wherein application of the second voltage to the PL together with driving the WL and the BL causes a second logic state to be programmed on the ferroelectric capacitor.

22 . The method according to claim 19 , wherein programming the ferroelectric capacitor comprises:
applying a first voltage to the PL to ensure that a polarization of the ferroelectric material corresponds to a first logic state, after applying the first voltage, applying a second voltage to the PL, the second voltage being insufficient to switch the polarization of the ferroelectric material, and driving the WL and the BL for a suitable duration to charge or discharge the intermediate node so that a charge on the

Assignees

• Intel Corp

Inventors

• Morris Daniel H
• Avci Uygar E
• Young Ian A

Classifications

• G11C11/2259

  Cell access · CPC title

• G11C11/2257

  Word-line or row circuits · CPC title

• G11C11/2273

  Reading or sensing circuits or methods · CPC title

• G11C11/2255

  Bit-line or column circuits · CPC title

• G11C11/221 Primary

  using ferroelectric capacitors · CPC title