Improved replacement electrode process for 3d ferroelectric memory

Patent metadata

Field	Value
Publication number	US-2024114696-A1
Application number	US-202217957603-A
Country	US
Kind code	A1
Filing date	Sep 30, 2022
Priority date	Sep 30, 2022
Publication date	Apr 4, 2024
Grant date	—

Abstract

Multiple-ferroelectric capacitor structures in memory devices, including in integrated circuit devices, and techniques for forming the structures. Insulators separating individual outer plates in a ferroelectric capacitor array are supported between wider portions of a shared, inner plate. Wider portions of an inner plate may be formed in lateral recesses between insulating layers. Ferroelectric material may be deposited over the inner plate between insulating layers after removing sacrificial layers. An etch-stop layer may protect the inner plate when sacrificial layers are removed. An etch-stop or interface layer may remain over the inner plate adjacent insulators.

First claim

We claim:

1 . An integrated circuit (IC) device, comprising:
a ferroelectric capacitor comprising:
a first plate, wherein a first insulator is above the first plate and a second insulator is below the first plate;
a second plate, wherein the second plate extends through the first plate and the first and second insulators, and a first width of a first portion of the second plate within the first plate is greater than both a second width of a second portion of the second plate within the second insulator and a third width of a third portion of the second plate within the first insulator; and
a ferroelectric layer between the first and the second plates, wherein a bottom surface of the first portion and a bottom surface of the ferroelectric layer adjoin with a top surface of the second insulator.

2 . The IC device of claim 1 , wherein the first or second insulator contacts a sidewall of the second plate.

3 . The IC device of claim 1 , wherein a bottom surface of the first plate is substantially coplanar with the bottom surface of the ferroelectric layer.

4 . The IC device of claim 1 , wherein the second plate is coupled to one or more access transistors, and the first plate is coupled to a plateline.

5 . A method, comprising:
forming an opening in an interleaved stack of insulator and sacrificial layers; recessing a sidewall of the sacrificial layers between the insulator layers; forming an inner plate in contact with the recessed sidewall and at least partially filling the opening; exposing a sidewall of the inner plate by removing the sacrificial layers; forming ferroelectric material on the exposed sidewall of the inner plate; and forming a plurality of ferroelectric capacitors by forming outer plates over the ferroelectric material.

6 . The method of claim 5 , wherein forming the opening comprises exposing a metallization structure coupled to a source or drain contact of an access transistor below the interleaved stack of insulator and sacrificial layers.

7 . The method of claim 5 , further comprising electrically isolating adjacent ferroelectric capacitors by recessing conductive material between laterally adjacent outer plates and forming an insulator in the recess.

8 . An integrated circuit (IC) device, comprising:
a first plate; a second plate, wherein the first plate extends through the second plate; a ferroelectric layer therebetween, wherein the first plate, the second plate, and the ferroelectric layer form a ferroelectric capacitor; and a first insulator above the second plate and a second insulator below the second plate, wherein an interface material is between the first plate and the first insulator and between the first plate and the second insulator.

9 . The IC device of claim 8 , wherein the ferroelectric layer contacts the first plate and the interface material is above and below the ferroelectric layer.

10 . The IC device of claim 8 , wherein the interface material comprises a dielectric material.

11 . The IC device of claim 8 , wherein the interface material is laterally between the first plate and the ferroelectric layer.

12 . The IC device of claim 11 , wherein the ferroelectric layer is between the first and second insulators.

13 . The IC device of claim 11 , wherein the interface material comprises a conductive material.

14 . The IC device of claim 8 , wherein the first plate is coupled to one or more select transistors, and the second plate is coupled to a plateline.

15 . A method, comprising:
forming an opening in an interleaved stack of insulator and sacrificial layers; forming an etch-stop layer over a sidewall of the opening; forming an inner plate over the etch-stop layer and at least partially filling the opening; exposing the etch-stop layer by removing the sacrificial layers; forming ferroelectric material between the insulator layers; and forming a plurality of ferroelectric capacitors by forming outer plates over the ferroelectric material.

16 . The method of claim 15 , further comprising removing the etch-stop layer between the insulator layers, wherein forming ferroelectric material comprises depositing ferroelectric material on an exposed sidewall of the inner plate.

17 . The method of claim 15 , wherein forming ferroelectric material comprises depositing ferroelectric material over the etch-stop layer.

18 . The method of claim 17 , wherein the etch-stop layer comprises a conductive material.

19 . The method of claim 15 , wherein forming the opening comprises exposing a metallization structure coupled to a source or drain contact of a select transistor below the interleaved stack of insulator and sacrificial layers.

20 . The method of claim 15 , further comprising electrically isolating adjacent ferroelectric capacitors by recessing conductive material between laterally adjacent outer plates and forming an insulator in the recess.

Assignees

• Intel Corp

Inventors

• Neumann Christopher
• Weinstein Cory
• Haratipour Nazila
• Doyle Brian
• Chang Sou-Chi
• Tronic Tristan
• Shivaraman Shriram
• Avci Uygar

Classifications

• H10D1/692

  Electrodes · CPC title

• H10D1/041

  of capacitors having no potential barriers · CPC title

• H10D1/682 Primary

  having dielectrics comprising perovskite structures · CPC title

• H01L27/11507 Primary

  Electricity · mapped topic

• H01L27/11514

  Electricity · mapped topic