Flash memory and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-2022130862-A1
Application number	US-202017077847-A
Country	US
Kind code	A1
Filing date	Oct 22, 2020
Priority date	Oct 22, 2020
Publication date	Apr 28, 2022
Grant date	—

Abstract

Provided is a flash memory includes a gate stack structure, a channel pillar, a first conductive pillar, a second conductive pillar, and a gate dielectric layer. The gate stack structure includes a plurality of gate layers electrically insulated from each other. Each gate layer includes a ferroelectric portion disposed between a sidewall of a first portion and a sidewall of a second gate portion. A thickness of the second gate portion is smaller than a thickness of the first gate portion. A channel pillar penetrates the gate stack structure. The first and second conductive pillars are disposed in the channel pillar. The first and second conductive pillars are separated from each other, and are each connected to the channel pillar. The gate dielectric layer is disposed between another sidewall of the first gate portion and the channel pillar.

First claim

What is claimed is:

1 . A flash memory, comprising:
a gate stack structure disposed on a dielectric base and includes a plurality of gate layers electrically insulated from each other, each gate layer comprising:
a first gate portion;
a second gate portion disposed adjacent to a sidewall of the first gate portion, wherein a thickness of the second gate portion is smaller than a thickness of the first gate portion;
a ferroelectric portion disposed between the sidewall of the first gate portion and a sidewall of the second gate portion; and
a channel pillar arranged on the dielectric base and penetrating the gate stack structure;
a first conductive pillar, and a second conductive pillar connected to the channel pillar and penetrating the gate stack structure, wherein the first conductive pillar and the second conductive pillar are separated from each other; and a gate dielectric layer disposed between another sidewall of the first gate portion and a sidewall of the channel pillar.

2 . The flash memory of claim 1 , wherein the second gate portion, the ferroelectric portion and the first gate portion has a first coupling area smaller than a second coupling area of the first gate portion, the gate dielectric portion and the channel pillar.

3 . The flash memory of claim 2 , wherein a ratio of the first coupling area to the second coupling area is between 0.2 and 0.5.

4 . The flash memory of claim 1 , wherein the ferroelectric portion has a dielectric constant greater than or equal to a dielectric constant of the gate dielectric layer.

5 . The flash memory of claim 1 , wherein the ferroelectric portion is a conformal layer.

6 . The flash memory of claim 1 , wherein the ferroelectric portion covers a top surface and a bottom surface of the second gate portion.

7 . The flash memory of claim 1 , further comprising a barrier layer located between the ferroelectric portion and the second gate portion.

8 . A flash memory, comprising:
a gate stack structure disposed on a substrate, comprising:
a first gate layer, comprising:
a first gate portion;
a second gate portion disposed adjacent to a sidewall of the first gate portion, wherein a thickness of the second gate portion is smaller than a thickness of the first gate portion; and
a ferroelectric portion disposed between the sidewall of the first gate portion and a sidewall of the second gate portion; and
a second gate layer located between the first gate layer and the substrate, and electrically insulated from the substrate and the first gate layer;
a channel structure penetrating the gate stack structure and electrically connected to the substrate; a first gate dielectric layer disposed between a sidewall of the channel structure and another sidewall of the first gate portion; and a second gate dielectric layer disposed between the sidewall of the channel structure and a sidewall of the second gate layer.

9 . The flash memory of claim 8 , wherein the second gate portion, the ferroelectric portion and the first gate portion have a first coupling area smaller than a second coupling area of the first gate portion, the first gate dielectric layer and the channel structure.

10 . The flash memory of claim 9 , wherein a ratio of the first coupling area to the second coupling area is between 0.2 and 0.5.

11 . The flash memory of claim 8 , wherein the ferroelectric portion has a dielectric constant greater than or equal to a dielectric constant of the first gate dielectric layer.

12 . The flash memory of claim 8 , wherein the ferroelectric portion is a conformal layer.

13 . The flash memory of claim 8 , further comprising:
a common source line penetrating the gate stack structure, and electrically connected to the substrate.

14 . The flash memory of claim 13 , further comprising:
an insulating liner layer located between the gate stack structure and the common source line.

15 . The flash memory of claim 8 , wherein the channel structure comprises:
a channel pillar penetrating the first gate layer, wherein an outer sidewall of the channel pillar is surrounded by the first gate dielectric layer; and a channel plug arranged under the channel pillar and penetrating the third gate layer, wherein a sidewall of the channel plug is surrounded by the second gate dielectric layer, a top surface of the channel plug is electrically connected to a bottom surface of the channel pillar, a bottom surface of the channel plug is electrically connected to the substrate.

16 . The flash memory of claim 8 , further comprising a barrier layer located between the ferroelectric portion and the second gate portion.

17 . The flash memory of claim 8 , wherein the ferroelectric portion covers a top surface and a bottom surface of the second gate portion.

18 . A method of fabricating flash memory, comprising:
forming an insulating stack structure on the dielectric base, the insulating stack structure comprising a plurality of insulating layers and a plurality of sacrificial layers alternately with each other; forming an opening in the insulating stack structure; removing portions of the plurality of sacrificial layers exposed by the opening so as to form a plurality of recesses; forming a plurality of first gate portions in the plurality of recesses; forming a gate dielectric layer on a sidewall of the opening to cover the plurality of first gate portions and the plurality of insulating layers; forming a channel layer in the opening to cover a sidewall of the gate dielectric layer; forming a first conductive pillar and a second conductive pillar in the openings, wherein the first conductive pillar and the second conductive pillar are separated from each other and electrically connected to the channel layer respectively; removing the plurality of sacrificial layers to form a plurality of lateral openings; forming a ferroelectric portion in each of the plurality of lateral openings to cover another sidewall of a corresponding first gate layer, and a top surface and a bottom surface of a corresponding lateral opening; and forming a second gate portion in each lateral opening, wherein a sidewall, a top surface, and a bottom surface of the second gate portion are covered by the ferroelectric portion.

19 . The method of claim 18 , wherein the second gate layer, the ferroelectric portion and the first gate portion has a first coupling area smaller than a second coupling area of the first gate portion, the gate dielectric layer and the channel layer.

20 . The method of claim 19 , wherein a ratio of the first coupling area to the second coupling area is between 0.2 and 0.5.

Assignees

• Macronix Int Co Ltd

Inventors

• Lue Hang-Ting

Classifications

• H10D30/701

  IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs · CPC title

• H10D64/689

  having ferroelectric layers · CPC title

• H10D64/512

  Disposition of the gate electrodes, e.g. buried gates · CPC title

• H10D30/6891

  characterised by the shapes, relative sizes or dispositions of the floating gate electrode · CPC title

• H10D64/033 Primary

  comprising ferroelectric layers · CPC title