Technologies for transistors with a thin-film ferroelectric

Patent metadata

Field	Value
Publication number	US-2024113220-A1
Application number	US-202217958094-A
Country	US
Kind code	A1
Filing date	Sep 30, 2022
Priority date	Sep 30, 2022
Publication date	Apr 4, 2024
Grant date	—

Abstract

Technologies for a transistor with a thin-film ferroelectric gate dielectric are disclosed. In the illustrative embodiment, a transistor has a thin layer of scandium aluminum nitride (ScxAl1-xN) ferroelectric gate dielectric. The channel of the transistor may be, e.g., gallium nitride or molybdenum disulfide. In one embodiment, the ferroelectric polarization changes when voltage is applied and removed from a gate electrode, facilitating switching of the transistor at a lower applied voltage. In another embodiment, the ferroelectric polarization of a gate dielectric of a transistor changes when the voltage is past a positive threshold value or a negative threshold value. Such a transistor can be used as a one-transistor memory cell.

First claim

1 . A device comprising:
a source region; a drain region; a channel between the source region and the drain region; a gate electrode; and a gate dielectric between the gate electrode and the channel, wherein the gate dielectric is ferroelectric, wherein the gate dielectric comprises scandium, aluminum, and nitrogen.

2 . The device of claim 1 , wherein the channel comprises gallium and nitrogen.

3 . The device of claim 1 , wherein the channel comprises molybdenum and sulfur.

4 . The device of claim 1 , wherein the device comprises a transistor, wherein the transistor comprises the source region, the drain region, the channel, the gate dielectric, and the gate electrode, wherein a threshold voltage of the transistor is less than 0.5 volts.

5 . The device of claim 1 , wherein the device comprises a transistor, wherein the transistor comprises the source region, the drain region, the channel, the gate dielectric, and the gate electrode,
wherein the transistor is a FinFET, a gate-all-around transistor, or a stacked gate-all-around-transistor.

6 . A processor comprising the device of claim 1 .

7 . A system comprising the processor of claim 6 and one or more memory devices.

8 . A device comprising:
a transistor, the transistor comprising a gate dielectric, wherein the gate dielectric is ferroelectric, wherein the gate dielectric comprises scandium, aluminum, and nitrogen.

9 . The device of claim 8 , wherein a threshold voltage of the transistor is less than 0.5 volts.

10 . The device of claim 8 , wherein the transistor comprises a channel, wherein the channel comprises gallium and nitrogen.

11 . The device of claim 8 , wherein the transistor comprises a channel, wherein the channel comprises molybdenum and sulfur.

12 . The device of claim 8 , wherein the transistor is a FinFET, a gate-all-around transistor, or a stacked gate-all-around-transistor.

13 . A processor comprising the device of claim 8 .

14 . A system comprising the processor of claim 13 and one or more memory devices.

15 . A device comprising:
a transistor comprising:
a source region;
a drain region;
a channel between the source region and the drain region;
a gate electrode; and
a gate dielectric between the gate electrode and the channel, wherein the gate dielectric comprises scandium, aluminum, and nitrogen,
wherein a threshold voltage of the transistor is less than 0.5 volts.

16 . The device of claim 15 , wherein the channel comprises gallium and nitrogen.

17 . The device of claim 15 , wherein the channel comprises molybdenum and sulfur.

18 . The device of claim 15 , wherein the transistor is a FinFET, a gate-all-around transistor, or a stacked gate-all-around-transistor.

19 . A processor comprising the device of claim 15 .

20 . A method comprising:
depositing a channel of a transistor; depositing a gate dielectric of the transistor, wherein the gate dielectric and the channel are adjacent, wherein the gate dielectric is ferroelectric, wherein the gate dielectric comprises scandium, aluminum, and nitrogen; and depositing a gate electrode of the transistor, wherein the gate electrode and the gate dielectric are adjacent.

21 . The method of claim 20 , wherein a threshold voltage of the transistor is less than 0.5 volts.

22 . The method of claim 20 , wherein the channel comprises gallium and nitrogen.

23 . The method of claim 20 , wherein the channel comprises molybdenum and sulfur.

24 . The method of claim 20 , wherein depositing the gate dielectric comprises depositing the gate dielectric with use of atomic layer deposition.

25 . The method of claim 20 , wherein depositing the channel comprises depositing the channel with use of atomic layer deposition.

Assignees

• Intel Corp

Inventors

• Sen Gupta Arnab
• Young Ian Alexander
• Nikonov Dmitri Evgenievich
• Radosavljevic Marko
• Metz Matthew V
• Plombon John J
• Kim Raseong
• Avci Uygar E
• O'Brien Kevin P
• Clendenning Scott B
• Retasket Jason C
• Shivaraman Shriram
• Adams Dominique A
• Rogan Carly
• Debashis Punyashloka
• Holybee Brandon
• Steinhardt Rachel A
• Lee Sudarat

Classifications

• H10P14/3436

  being chalcogenide semiconductor materials not being oxides, e.g. ternary compounds · CPC title

• H10P14/3416

  Nitrides · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D64/689 Primary

  having ferroelectric layers · CPC title