Semiconductor element and method for manufacturing same

Patent metadata

Field	Value
Publication number	US-2022271220-A1
Application number	US-202017624954-A
Country	US
Kind code	A1
Filing date	Jun 30, 2020
Priority date	Jul 8, 2019
Publication date	Aug 25, 2022
Grant date	—

Abstract

The present invention relates to a semiconductor element and a method for manufacturing same, wherein the semiconductor element may comprise: a base element, an intermediate layer formed in at least one direction of the base element; and a metal layer formed on the intermediate layer in a direction opposite to the base element, and wherein a conductive filament may be formed inside the intermediate layer according to the application of a voltage to the intermediate layer.

First claim

What is claimed is:

1 . A semiconductor element comprising:
a base element; an intermediate layer formed in at least one direction of the base element; and a metal layer formed on the intermediate layer in a direction opposite to the base element, wherein a conducting filament is formed in an inner space of the intermediate layer according to application of a voltage to the intermediate layer.

2 . The semiconductor element of claim 1 , wherein the conducting filament in the inner space of the intermediate layer is reduced or removed according to application of a voltage with a polarity opposite to that of the voltage applied to the intermediate layer.

3 . The semiconductor element of claim 1 , wherein magnitude of on-current increases according to formation of the conducting filament.

4 . The semiconductor element of claim 1 , wherein a thickness of the intermediate layer has a value between 2 nanometers (nm) and 4 nm.

5 . The semiconductor element of claim 1 , wherein the intermediate layer is formed in at least one direction of the base element using an atomic layer deposition (ALD) process.

6 . The semiconductor element of claim 1 , wherein the intermediate layer includes a dielectric, and the dielectric includes at least one of hafnium oxide (HfO 2 ), silicon dioxide (SiO 2 ), silicon nitride (SiN), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), zirconium dioxide (ZrO 2 ), and zinc oxide (ZnO).

7 . The semiconductor element of claim 1 , wherein the base element includes a substrate and a source installed in one direction of the substrate,
the intermediate layer includes a first intermediate layer installed to correspond to the source, and the metal layer includes a first metal layer formed to correspond to the first intermediate layer.

8 . The semiconductor element of claim 1 , wherein the base element includes a metal-oxide-semiconductor field effect transistor (MOSFET), a fin field effect transistor (FinFET), a high electron mobility transistor (HEMT), and a junction field effect transistor (JFET).

9 . A method of manufacturing a semiconductor element, the method comprising:
forming one or more intermediate layers on a base element; and forming a metal layer corresponding to the one or more intermediate layers on the one or more intermediate layers, wherein a conducting filament is formed in an inner space of the intermediate layer according to application of a voltage to the intermediate layer.

Assignees

• Univ Korea Res & Bus Found

Inventors

• Yu Hyun-Yong
• Kim Seung-Hwan

Classifications

• H10W20/01

  Manufacture or treatment · CPC title

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10D30/831

  Vertical FETs having PN junction gate electrodes (Vertical SIT H10D30/202) · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/47

  having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT] · CPC title