Resistive memory devices with a cavity between electrodes

Patent metadata

Field	Value
Publication number	US-2024049611-A1
Application number	US-202217817430-A
Country	US
Kind code	A1
Filing date	Aug 4, 2022
Priority date	Aug 4, 2022
Publication date	Feb 8, 2024
Grant date	—

Abstract

The disclosed subject matter relates generally to resistive memory devices and methods of forming the same. More particularly, the present disclosure relates to two terminal and three terminal resistive random-access (ReRAM) memory devices with a cavity arranged between electrodes.

First claim

What is claimed is:

1 . A resistive memory device comprising:
a first dielectric pillar having an upper surface; a second dielectric pillar adjacent to the first dielectric pillar, the second dielectric pillar having an upper surface; a first bottom electrode having a top segment on the upper surface of the first dielectric pillar, the top segment of the first bottom electrode includes an upper surface and a side surface, the side surface of the top segment meets the upper surface of the top segment to provide a first bottom electrode top edge; a second bottom electrode having a top segment disposed on the upper surface of the second dielectric pillar, the top segment of the second bottom electrode includes an upper surface and a side surface, the side surface of the top segment meets the upper surface of the top segment to provide a second bottom electrode top edge; a switching layer laterally between the first bottom electrode and the second bottom electrode, the switching layer is in direct contact with the first bottom electrode top edge and the second bottom electrode top edge; and a cavity defined laterally between the first dielectric pillar and the second dielectric pillar, the cavity is bounded by at least the first bottom electrode, the second bottom electrode, and the switching layer, wherein the switching layer is positioned over the cavity.

2 . The resistive memory device of claim 1 , wherein the first bottom electrode top edge and the second bottom electrode top edge form overhangs extending over the cavity.

3 . The resistive memory device of claim 1 , further comprising a top electrode positioned on the switching layer.

4 . The resistive memory device of claim 3 , wherein the top electrode includes a bottom surface and a protrusion extending from the bottom surface of the top electrode into the switching layer.

5 . The resistive memory device of claim 4 , wherein the switching layer and the top electrode extend laterally over the first dielectric pillar and the second dielectric pillar.

6 . The resistive memory device of claim 1 , wherein the switching layer extends laterally over the first dielectric pillar and the second dielectric pillar.

7 . The resistive memory device of claim 1 , wherein the first dielectric pillar has side surfaces, the second dielectric pillar has side surfaces, the first bottom electrode has a bottom segment on the side surfaces of the first dielectric pillar, and the second bottom electrode has a bottom segment of the side surfaces of the second dielectric pillar.

8 . The resistive memory device of claim 1 , further comprising an interlayer dielectric below the first dielectric pillar and the second dielectric pillar, wherein the first dielectric pillar and the second dielectric pillar are integrally formed with the interlayer dielectric.

9 . The resistive memory device of claim 1 , wherein the side surface of the top segment of the first bottom electrode forms an acute angle with the upper surface of the top segment of the first bottom electrode and the side surface of the top segment of the second bottom electrode forms an acute angle with the upper surface of the top segment of the second bottom electrode.

10 . A resistive memory device comprising:
a first dielectric pillar having an upper surface; a second dielectric pillar adjacent to the first dielectric pillar, the second dielectric pillar having an upper surface; a first dielectric cap on the upper surface of the first dielectric pillar; a second dielectric cap on the upper surface of the second dielectric pillar; a first bottom electrode having a top segment covering the first dielectric cap, the top segment of the first bottom electrode includes an upper surface and a side surface, the side surface of the top segment meets the upper surface of the top segment to provide a first bottom electrode top edge; a second bottom electrode having a top segment covering the second dielectric cap, the top segment of the second bottom electrode includes an upper surface and a side surface, the side surface of the top segment meets the upper surface of the top segment to provide a second bottom electrode top edge; a switching layer laterally between the first bottom electrode and the second bottom electrode, the switching layer is in direct contact with the first bottom electrode top edge and the second bottom electrode top edge; and a cavity defined laterally between the first dielectric pillar and the second dielectric pillar, the cavity is bounded by at least the first bottom electrode, the second bottom electrode, and the switching layer, wherein the switching layer is positioned over the cavity.

11 . The resistive memory device of claim 10 , wherein the first bottom electrode top edge and the second bottom electrode top edge form overhangs extending over the cavity.

12 . The resistive memory device of claim 10 , wherein the first dielectric cap includes an upper surface and a side surface, the side surface of the first dielectric cap forms an acute angle with the upper surface of the first dielectric cap, and the second dielectric cap includes an upper surface and a side surface, the side surface of the second dielectric cap forms an acute angle with the upper surface of the second dielectric cap.

13 . The resistive memory device of claim 12 , wherein the first bottom electrode has a bottom segment on the side surface of the first dielectric cap and the second bottom electrode has a bottom segment of the side surface of the second dielectric cap.

14 . The resistive memory device of claim 13 , wherein the first dielectric pillar has side surfaces, the second dielectric pillar has side surfaces, the bottom segment of the first bottom electrode extends to lie on the side surfaces of the first dielectric pillar, and the bottom segment of the second bottom electrode extends to lie on the side surfaces of the second dielectric pillar.

15 . The resistive memory device of claim 10 , further comprising a top electrode positioned on the switching layer.

16 . The resistive memory device of claim 15 , wherein the top electrode includes a bottom surface and a protrusion extending from the bottom surface of the top electrode into the switching layer.

17 . The resistive memory device of claim 16 , wherein the switching layer and the top electrode extend laterally over the first dielectric pillar and the second dielectric pillar.

18 . The resistive memory device of claim 10 , wherein the switching layer extends laterally over the first dielectric pillar and the second dielectric pillar.

19 . The resistive memory device of claim 10 , further comprising an interlayer dielectric below the first dielectric pillar and the second dielectric pillar, wherein the first dielectric pillar and the second dielectric pillar are integrally formed with the interlayer dielectric.

20 . The resistive memory device of claim 10 , wherein the side surface of the top segment of the first bottom electrode forms an acute angle with the upper surface of the top segment of the first bottom electrode, and the side surface of the top segment of the second bottom electrode forms an acute angle with the upper surface of the top segment of the second bottom electrode.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Hsieh Curtis Chun-I
• Tan Juan Boon
• Hsu Wei-Hui
• Yi Wanbing
• Kang Kai

Classifications

• H01L45/1233 Primary

  Electricity · mapped topic

• H01L45/1253

  Electricity · mapped topic

• H01L27/2481

  Electricity · mapped topic

• H10N70/826 Primary

  adapted for essentially vertical current flow, e.g. sandwich or pillar type devices · CPC title

• H10B63/84

  arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays · CPC title