Chip package and method of forming a chip package

Patent metadata

Field	Value
Publication number	US-2023395532-A1
Application number	US-202318236858-A
Country	US
Kind code	A1
Filing date	Aug 22, 2023
Priority date	May 29, 2020
Publication date	Dec 7, 2023
Grant date	—

Abstract

A chip package is provided. The chip package may include at least one chip, an exposed metal region and a metal protection layer structure over the exposed metal region and configured to protect the metal region from oxidation. The protection layer structure includes a low-temperature deposited oxide, and a hydrothermally converted metal oxide layer over the protection layer structure.

First claim

1 - 20 . (canceled)

21 . A chip package, comprising:
at least one chip; an exposed metal region and non-metal region; a metal protection layer structure over the exposed metal region and non-metal region, the protection layer structure comprising a low-temperature deposited oxide; and a hydrothermally converted metal oxide layer over the protection layer structure.

22 . The chip package according to claim 21 ,
wherein the low-temperature deposited oxide comprises or consists of a metal oxide.

23 . The chip package according to claim 21 ,
wherein the hydrothermally converted metal oxide layer comprises or consists of an aluminum hydroxide layer.

24 . A chip package, comprising:
at least one chip; an exposed metal region and non-metal region; a metal protection layer structure over the exposed metal region and non-metal region, and configured to protect the metal region from oxidation; a hydrothermally converted metal oxide layer over the protection layer structure; and an aluminum oxide layer between the metal protection layer structure and the hydrothermally converted metal oxide layer.

25 . The chip package according to claim 21 ,
wherein the metal protection layer structure comprises a top layer comprising at least one of a group of materials, the group consisting of:
silicon dioxide;
titanium dioxide;
zinc oxide;
hafnium dioxide;
tantalum pentoxide; and
zirconium dioxide.

26 . The chip package according claim 25 ,
wherein the metal protection layer structure comprises an aluminum oxide layer between the top layer and the exposed metal region.

27 . The chip package according to claim 21 ,
wherein the metal protection layer structure comprises aluminum oxide with a top layer of doped aluminum oxide.

28 . The chip package according to claim 21 ,
wherein the exposed metal region comprises at least one of a group of metal regions, the group consisting of:
a chip pad;
a leadframe;
a wire bond;
a clip; and
a stripe bond.

29 . The chip package according to claim 21 ,
wherein the exposed metal region comprises at least one of a group of materials, the group consisting of:
copper (Cu);
nickel (Ni);
nickel-phosphorus (NiP);
aluminum (Al);
gold (Au);
silver (Ag);
palladium (Pd); and
alloys thereof, for example PdAuAg.

30 . The chip package according to claim 21 , further comprising:
an encapsulation material attached to at least a portion of the exposed metal region by the metal protection layer structure and the hydrothermally converted metal oxide layer.

31 . The chip package according to claim 30 , further comprising:
a non-metal layer; wherein the encapsulation material is further attached to at least a portion of the non-metal layer.

32 . A chip package, comprising:
at least one chip positioned on a leadframe surface; an exposed metal region and non-metal region on a surface of the at least one chip; a metal protection layer structure over the exposed metal region and non-metal region, the protection layer structure comprising a metal oxide; and a hydrothermally converted metal oxide layer over the protection layer structure.

33 . The chip package according to claim 32 ,
wherein the metal oxide comprises an aluminum oxide.

34 . The chip package according to claim 32 ,
where the hydrothermally converted metal oxide layer comprises an aluminum hydroxide layer.

35 . The chip package of claim 32 , where the metal protection layer structure comprises a multilayer formed by a plurality of single layers.

36 . The chip package of claim 35 , where one or more of the plurality of single layers are made of different material.

37 . The chip package of claim 32 , where the metal protection layer structure is an adhesion layer structure.

38 . The chip package of claim 32 , where the metal protection layer structure includes a moisture resistant doped region that is doped with silicon.

39 . The chip package of claim 32 , further comprising:
an encapsulation material attached to at least a portion of the exposed metal region and non-metal region by the metal protection layer structure and the hydrothermally converted metal oxide layer.

40 . The chip package of claim 32 , where the metal protection layer structure and the hydrothermally converted metal oxide layer extend directly over the leadframe surface.

Assignees

• Infineon Technologies Ag

Inventors

• Sax Harry Walter
• Gatterbauer Johann
• Lehnert Wolfgang
• Napetschnig Evelyn
• Rogalli Michael

Classifications

• H10W72/953

  not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/019

  of bond pads · CPC title

• H10W74/127

  characterised by arrangements for sealing or adhesion · CPC title

• H10W74/01

  Manufacture or treatment · CPC title