Sram bit cells with three-dimensional integration

Patent metadata

Field	Value
Publication number	US-2023238342-A1
Application number	US-202217584507-A
Country	US
Kind code	A1
Filing date	Jan 26, 2022
Priority date	Jan 26, 2022
Publication date	Jul 27, 2023
Grant date	—

Abstract

Structures for a static random access memory bit cell and methods of forming a structure for a static random access memory bit cell. The structure includes a first field-effect transistor on a first substrate and a second field-effect transistor on a second substrate. The first field-effect transistor includes a first gate, and the second field-effect transistor includes a second gate. The structure further includes a first interconnect structure on the first substrate and a second interconnect structure on the second substrate. The first interconnect structure includes a first metal feature connected to the first gate, and the first metal feature has a first surface. The second interconnect structure includes a second metal feature connected to the second gate, and the second metal feature has a second surface that is connected to the first surface of the first metal feature.

First claim

What is claimed is:

1 . A structure for a static random access memory bitcell, the structure comprising:
a first substrate; a second substrate; a first field-effect transistor on the first substrate, the first field-effect transistor including a first gate; a second field-effect transistor on the second substrate, the second field-effect transistor including a second gate; a first interconnect structure on the first substrate, the first interconnect structure including a first metal feature connected to the first gate, and the first metal feature having a first surface; and a second interconnect structure on the second substrate, the second interconnect structure including a second metal feature connected to the second gate, and the second metal feature including a second surface that is connected to the first surface of the first metal feature.

2 . The structure of claim 1 wherein the first interconnect structure includes a third metal feature having a third surface, and the second interconnect structure includes a fourth metal feature having a fourth surface that is connected to the third surface of the third metal feature.

3 . The structure of claim 2 further comprising:
a third field-effect transistor on the first substrate, the third field-effect transistor including a third gate connected to the third metal feature; and
a fourth field-effect transistor on the second substrate, the fourth field-effect transistor including a fourth gate connected to the fourth metal feature.

4 . The structure of claim 3 wherein the third field-effect transistor includes a source/drain region, and the third metal feature is further connected to the source/drain region.

5 . The structure of claim 4 wherein the first field-effect transistor and the third field-effect transistor are p-type metal-oxide-semiconductor transistors, and the second field-effect transistor and the fourth field-effect transistor are n-type metal-oxide-semiconductor transistors.

6 . The structure of claim 1 wherein the first field-effect transistor includes a source/drain region, and the first metal feature is further connected to the source/drain region.

7 . The structure of claim 6 wherein the first field-effect transistor is a p-type metal-oxide-semiconductor transistor, and the second field-effect transistor is an n-type metal-oxide-semiconductor transistor.

8 . The structure of claim 1 wherein the first interconnect structure includes a third metal feature, and further comprising:
an inter-tier via extending through the first substrate to the third metal feature.

9 . The structure of claim 8 wherein the first metal feature and the third metal feature are positioned in different metallization levels of the first interconnect structure.

10 . The structure of claim 1 wherein the second interconnect structure includes a third metal feature, and further comprising:
an inter-tier via extending through the first substrate and the first interconnect structure to the third metal feature.

11 . The structure of claim 10 wherein the second metal feature and the third metal feature are positioned in different metallization levels of the second interconnect structure.

12 . The structure of claim 1 wherein the first interconnect structure includes a third metal feature and a fourth metal feature, and further comprising:
a bit line connected to the third metal feature; and
a ground line connected to the fourth metal feature,
wherein the first metal feature is laterally offset from the third metal feature and the fourth metal feature.

13 . The structure of claim 12 wherein the ground line is aligned transverse to the bit line and parallel to the first gate.

14 . The structure of claim 13 wherein the first gate is aligned transverse to the ground line, and the bit line is aligned transverse to the first gate.

15 . The structure of claim 1 wherein the second interconnect structure includes a third metal feature, and further comprising:
a supply voltage line connected to the third metal feature,
wherein the first metal feature is laterally offset relative to the third metal feature.

16 . A method of forming a structure for a static random access memory bitcell, the method comprising:
forming a first field-effect transistor on a first substrate, wherein the first field-effect transistor includes a first gate; forming a second field-effect transistor on a second substrate, wherein the second field-effect transistor includes a second gate; forming a first interconnect structure on the first substrate, wherein the first interconnect structure includes a first metal feature connected to the first gate; forming a second interconnect structure on the second substrate, wherein the second interconnect structure includes a second metal feature connected to the second gate; and bonding a first surface of the first metal feature to a second surface of the second metal feature.

17 . The method of claim 16 wherein bonding the first surface of the first metal feature to the second surface of the second metal feature comprises:
forming a metal-to-metal bond between the first surface of the first metal feature and the second surface of the second metal feature.

18 . The method of claim 16 wherein the first interconnect structure includes a third metal feature, the second interconnect structure includes a fourth metal feature, and further comprising:
bonding a third surface of the third metal feature to a fourth surface of the fourth metal feature by a metal-to-metal bond.

19 . The method of claim 18 further comprising:
forming a third field-effect transistor on the first substrate, wherein the third field-effect transistor includes a third gate connected to the third metal feature;
forming a fourth field-effect transistor on the second substrate, wherein the fourth field-effect transistor includes a fourth gate connected to the fourth metal feature.

20 . The method of claim 19 wherein the third field-effect transistor includes a source/drain region, and the third metal feature is further connected to the source/drain region.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Balan Hari
• Tan Juan Boon
• Chockalingam Ramasamy
• Yi Wanbing

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title