Semiconductor Device and Method

Patent metadata

Field	Value
Publication number	US-2023121210-A1
Application number	US-202217710457-A
Country	US
Kind code	A1
Filing date	Mar 31, 2022
Priority date	Oct 12, 2021
Publication date	Apr 20, 2023
Grant date	—

Abstract

An improved method of forming conductive features and a semiconductor device formed by the same are disclosed. In an embodiment, a method includes forming a metal line extending through a first dielectric layer, the metal line being electrically coupled to a transistor; selectively depositing a sacrificial material over the metal line; selectively depositing a first dielectric material over the first dielectric layer and adjacent to the sacrificial material; selectively depositing a second dielectric material over the first dielectric material; removing the sacrificial material to form a first recess exposing the metal line; and forming a metal via in the first recess and electrically coupled to the metal line.

First claim

1 . A method comprising:
forming a metal line extending through a first dielectric layer, wherein the metal line is electrically coupled to a transistor; selectively depositing a sacrificial material over the metal line; selectively depositing a first dielectric material over the first dielectric layer and adjacent to the sacrificial material; selectively depositing a second dielectric material over the first dielectric material; removing the sacrificial material to form a first recess exposing the metal line; and forming a metal via in the first recess and electrically coupled to the metal line.

2 . The method of claim 1 , further comprising etching back the sacrificial material after selectively depositing the first dielectric material, wherein the second dielectric material is deposited along a top surface and a side surface of the first dielectric material.

3 . The method of claim 2 , wherein the sacrificial material is etched back using an oxygen plasma.

4 . The method of claim 2 , wherein the sacrificial material is deposited at least partially on the first dielectric layer, and wherein portions of the sacrificial material extending on the first dielectric layer are removed by etching back the sacrificial material.

5 . The method of claim 1 , further comprising:
depositing a second dielectric layer over the second dielectric material and the sacrificial material; and etching the second dielectric layer before removing the sacrificial material.

6 . The method of claim 1 , further comprising:
depositing a second dielectric layer over the second dielectric material, the first dielectric material, and the metal line after removing the sacrificial material; and etching the second dielectric layer before forming the metal via.

7 . The method of claim 1 , wherein the sacrificial material is removed using an oxygen plasma.

8 . The method of claim 1 , wherein the first dielectric material has a first dielectric constant less than a second dielectric constant of the second dielectric material.

9 . A method comprising:
forming a first conductive feature in a first dielectric layer, wherein the first conductive feature is electrically coupled to a transistor; selectively depositing a first dielectric material over the first dielectric layer; selectively depositing a sacrificial material over the first conductive feature and adjacent to the first dielectric material; selectively depositing a second dielectric material over the first dielectric material, wherein a first dielectric constant of the first dielectric material is less than a second dielectric constant of the second dielectric material; depositing a second dielectric layer over the second dielectric material, the first dielectric material, and the first conductive feature; etching the second dielectric layer to form a first recess; and forming a second conductive feature in the first recess and electrically coupled to the transistor.

10 . The method of claim 9 , further comprising etching back the first dielectric material before selectively depositing the second dielectric material.

11 . The method of claim 10 , further comprising removing the sacrificial material after etching the second dielectric layer to form the first recess.

12 . The method of claim 10 , wherein a first top surface of the sacrificial material is level with a second top surface of the second dielectric material after selectively depositing the second dielectric material.

13 . The method of claim 9 , further comprising removing the sacrificial material before depositing the second dielectric layer.

14 . The method of claim 9 , further comprising removing the sacrificial material using an oxygen plasma.

15 . A semiconductor device comprising:
a first dielectric layer over a semiconductor substrate; a metal line extending through the first dielectric layer and electrically coupled to a transistor; a second dielectric layer extending along a first top surface of the first dielectric layer; a third dielectric layer extending along opposite sidewalls and a second top surface of the second dielectric layer; a fourth dielectric layer extending along a third top surface of the third dielectric layer; and a metal via extending through the fourth dielectric layer and the third dielectric layer, wherein the metal via is electrically coupled to the metal line, wherein the metal via extends along the third top surface of the third dielectric layer, wherein the third dielectric layer separates the second dielectric layer from the metal via.

16 . The semiconductor device of claim 15 , wherein the second dielectric layer has a first dielectric constant less than a second dielectric constant of the third dielectric layer.

17 . The semiconductor device of claim 15 , wherein the second dielectric layer has a first thickness ranging from 20 Å to 30 Å, and wherein the third dielectric layer has a thickness ranging from 5 Å to 15 Å.

18 . The semiconductor device of claim 15 , wherein a first portion of the metal via extending through the fourth dielectric layer has a tapered shape, and wherein a second portion of the metal via extending through the third dielectric layer has a reverse tapered shape.

19 . The semiconductor device of claim 15 , wherein a first portion of the metal via extending through the fourth dielectric layer has a tapered shape, and wherein a second portion of the metal via extending through the third dielectric layer has vertical sidewalls extending in a direction perpendicular to a major surface of the semiconductor substrate.

20 . The semiconductor device of claim 15 , further comprising a sacrificial material extending through the third dielectric layer, the sacrificial material comprising a polymer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Wei-Ren
• Wang Jen Hung
• Lee Tze-Liang

Classifications

• H10P14/3452

  Microstructure · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/0696

  by using sacrificial placeholders, e.g. using sacrificial plugs · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title