Fin field effect transistor having airgap and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-2020043796-A1
Application number	US-201916286558-A
Country	US
Kind code	A1
Filing date	Feb 26, 2019
Priority date	Jul 31, 2018
Publication date	Feb 6, 2020
Grant date	—

Abstract

A method of manufacturing a FinFET includes at last the following steps. A semiconductor substrate is patterned to form trenches in the semiconductor substrate and semiconductor fins located between two adjacent trenches of the trenches. Gate stacks is formed over portions of the semiconductor fins. Strained material portions are formed over the semiconductor fins revealed by the gate stacks. First metal contacts are formed over the gate stacks, the first metal contacts electrically connecting the strained material portions. Air gaps are formed in the FinFET at positions between two adjacent gate stacks and between two adjacent strained materials.

First claim

What is claimed is:

1 . A method of manufacturing a fin field effect transistor (FinFET), comprising:
patterning a semiconductor substrate to form trenches in the semiconductor substrate and semiconductor fins located between two adjacent trenches of the trenches; forming gate stacks over portions of the semiconductor fins; forming strained material portions over the semiconductor fins revealed by the gate stacks; forming first metal contacts over the gate stacks, the first metal contacts electrically connecting the strained material portions; and forming air gaps in the FinFET at positions between two adjacent gate stacks of the gate stacks.

2 . The method of claim 1 , prior to forming the first metal contacts over the gate stacks, the method further comprising:
forming an interlayer dielectric layer to fill gaps between the gate stacks and the strained material portions; forming a first dielectric material over the interlayer dielectric layer; patterning the first dielectric material to form first trenches therein, the first trenches respectively exposing the gate stacks; and disposing a high-k dielectric material to fill up the first trenches and forming hard mask portions inside the first trenches.

3 . The method of claim 2 , after forming the hard mask portions, the method further comprising:
patterning the first dielectric material to form first openings exposing the strained material portions; and filling a first conductive material in the first openings to form the first metal contacts.

4 . The method of claim 3 , after forming the hard mask portions, the method further comprising:
patterning the hard mask portions to form second openings exposing the gate stacks; and filling a second conductive material in the second openings to form second metal contacts connecting to the gate stacks.

5 . The method of claim 3 , wherein after forming the first metal contacts, the method further comprising:
forming a patterned hard mask layer on the first dielectric layer removing a portion of the first metal contacts to form second trenches exposing the first dielectric material; removing the first dielectric material the interlayer dielectric layer to form the air gaps; and forming a third dielectric material to seal the second trenches located between the patterned hard mask layer and the first metal contacts, wherein the third dielectric material is formed above the air gaps and at sidewalls of the air gaps.

6 . The method of claim 3 , after forming the first metal contacts, the method further comprising:
forming a second dielectric material over the first dielectric material and the hard mask portions; and patterning the second dielectric material to form third openings and fourth openings therein, the third openings respectively exposing the first metal contacts; and forming conductive structures on the second dielectric material, wherein some of the conductive structures extend into the third openings to electrically connect to the strained material portions through the first metal contacts.

7 . The method of claim 6 , wherein after forming the conductive structures, the method further comprising:
removing the second dielectric material; etching the first dielectric material to form openings exposing the interlayer dielectric layer underlying thereof; removing the interlayer dielectric layer to form the air gaps; and forming a third dielectric material to seal the openings formed in the first dielectric material.

8 . The method of claim 7 , wherein the third dielectric material is formed above the air gaps.

9 . The method of claim 6 , wherein the third dielectric material is formed above the air gaps and at sidewalls of the air gaps.

10 . A method of manufacturing a fin field effect transistor (FinFET), comprising:
providing a semiconductor substrate; patterning the semiconductor substrate to form trenches in the semiconductor substrate and semiconductor fins located between two adjacent trenches of the trenches; forming insulators in the trenches, respectively; forming dummy gate stacks over portions of the semiconductor fins and portions of the insulators; forming strained material portions over the semiconductor fins revealed by the dummy gate stacks; replacing the dummy gate stacks with gate stacks; forming first metal contacts over the gate stacks, the first metal contacts electrically connecting the strained material portions; forming second metal contacts over the gate stacks, the second metal contacts electrically connecting the gate stacks; and forming air gaps in the FinFET at positions between two adjacent gate stacks of the gate stacks.

11 . The method of claim 10 , prior to replacing the dummy gate stack with the gate stacks, the method further comprising:
forming an interlayer dielectric layer to wrap the dummy gate stacks and the strained material portions, wherein the dummy gate stacks are exposed by the interlayer dielectric layer, and the dummy gate stacks exposed by the interlayer dielectric layer are replacing with the gate stacks.

12 . The method of claim 11 , prior to forming the first metal contacts and forming the second metal contacts, the method further comprising:
forming a first dielectric material over the interlayer dielectric layer; patterning the first dielectric material to form first trenches therein, the first trenches respectively exposing the gate stacks; and disposing a high-k dielectric material to fill up the first trenches and forming hard mask portions inside the first trenches.

13 . The method of claim 12 , after forming the hard mask portions, the method further comprising:
patterning the first dielectric material to form first openings exposing the strained material portions; patterning the hard mask portions to form second openings exposing the gate stacks; filling a first conductive material in the first openings to form the first metal contacts; and filling a second conductive material in the second openings to form the second metal contacts.

14 . The method of claim 12 , after forming the first metal contacts and forming the second metal contacts, the method further comprising:
forming a second dielectric material over the first dielectric material and the hard mask portions; and patterning the second dielectric material to form third openings and fourth openings therein, the third openings respectively exposing the first metal contacts, and the fourth openings respectively exposing the second metal contacts; and forming conductive structures on the second dielectric material, wherein some of the conductive structures extend into the third openings to connect to the first metal contacts, and some of the conductive structures extend into the fourth openings to connect to the second metal contacts.

15 . The method of claim 14 , wherein after forming the conductive structures, the method further comprising:
removing the second dielectric material; etching the first dielectric material to form openings exposing the interlayer dielectric layer underlying thereof; removing the interlayer dielectric layer to form the air gaps; and forming a third dielectric material to seal the openings formed in the first dielectric material.

16 . The method of claim 15 , wherein the third dielectric material is formed above the air gaps.

17 . The method of claim 15 , wherein the third dielectric material is formed above the air gaps and at sidewalls of the air gaps.

18 . A fin field effect transistor (FinFET), comprisi

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yeong Sai-Hooi
• LEE Kai-Hsuan
• Lin Yu-Ming
• Chui Chi-On

Classifications

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W10/021

  of air gaps · CPC title

• H10W10/20

  Air gaps · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title