Interconnect structure and method

Patent metadata

Field	Value
Publication number	US-2021343588-A1
Application number	US-202017039390-A
Country	US
Kind code	A1
Filing date	Sep 30, 2020
Priority date	Apr 29, 2020
Publication date	Nov 4, 2021
Grant date	—

Abstract

An embodiment is a method including forming an opening in a mask layer, the opening exposing a conductive feature below the mask layer, forming a conductive material in the opening using an electroless deposition process, the conductive material forming a conductive via, removing the mask layer, forming a conformal barrier layer on a top surface and sidewalls of the conductive via, forming a dielectric layer over the conformal barrier layer and the conductive via, removing the conformal barrier layer from the top surface of the conductive via, and forming a conductive line over and electrically coupled to the conductive via.

First claim

What is claimed is:

1 . A method comprising:
forming an opening in a mask layer, the opening exposing a conductive feature below the mask layer; forming a conductive material in the opening using an electroless deposition process, the conductive material forming a conductive via; removing the mask layer; forming a conformal barrier layer on a top surface and sidewalls of the conductive via; forming a dielectric layer over the conformal barrier layer and the conductive via; removing the conformal barrier layer from the top surface of the conductive via; and forming a conductive line over and electrically coupled to the conductive via.

2 . The method of claim 1 , wherein the conductive line physically contacts top surfaces of the conductive via and the conformal barrier layer.

3 . The method of claim 1 , wherein forming the conformal barrier layer comprises:
performing an atomic layer deposition process, the atomic layer deposition process forming the conformal barrier layer.

4 . The method of claim 1 , wherein the conformal barrier layer is not between the conductive via and the conductive feature.

5 . The method of claim 1 , wherein forming the conductive line comprises:
forming a second opening in the dielectric layer, wherein forming the second opening removes the conformal barrier layer from the top surface of the conductive via; forming a second barrier layer in the second opening; forming a seed layer on the second barrier layer; and forming a second conductive material on the seed layer in the second opening.

6 . The method of claim 1 further comprising:
planarizing the dielectric layer, the conformal barrier layer, and the conductive via to expose the top surface of the conductive via, wherein planarizing the dielectric layer removes the conformal barrier layer from the top surface of the conductive via;
forming a second dielectric layer over the planarized dielectric layer, the planarized conformal barrier layer, and the planarized conductive via;
forming a second opening in the second dielectric layer, the top surface of the conductive via being exposed in the second opening; and
forming the conductive line in the second opening.

7 . The method of claim 1 , wherein the conductive material of the conductive via comprises copper.

8 . The method of claim 1 , wherein forming the conductive material in the opening using an electroless deposition process further comprises:
performing a first electroless deposition process to form a first conductive material in the opening, the first conductive material partially filling the opening; and performing a second electroless deposition process to form a second conductive material on the first conductive material in the opening, the first conductive material being different than the second conductive material.

9 . The method of claim 8 , wherein the first conductive material is copper, and the second conductive material is cobalt.

10 . A method comprising:
forming a first device on a substrate, the first device comprising a gate electrode on the substrate with source/drain regions on opposite sides of the gate electrode; forming a first dielectric layer over the first device and the substrate; forming conductive contacts in the first dielectric layer and electrically coupled to the gate electrode and source/drain regions of the first device; forming a photoresist over the first dielectric layer and the conductive contacts; forming first openings within the photoresist, the conductive contacts being exposed in the first openings; performing an electroless deposition process forming a conductive material in the first openings, the conductive material in the first openings forming conductive vias in the first openings; removing the photoresist; conformally depositing a barrier layer on top surfaces and sidewalls of conductive vias; forming a second dielectric layer over the conductive vias; removing a portion of the barrier layer to expose top surfaces of the conductive vias; and forming conductive lines over and coupled to the top surfaces of the conductive vias.

11 . The method of claim 10 , wherein the barrier layer extends from the first dielectric layer to the conductive lines.

12 . The method of claim 11 , wherein the barrier layer is not between the conductive contacts and the conductive vias.

13 . The method of claim 10 , wherein performing the electroless deposition process forming the conductive material in the first openings further comprises:
performing a first electroless deposition process to form a first conductive material in the first opening, the first conductive material partially filling the first openings; and performing a second electroless deposition process to form a second conductive material on the first conductive material in the first opening, the first conductive material being different than the second conductive material.

14 . The method of claim 13 , wherein the first conductive material is copper, and the second conductive material is cobalt.

15 . The method of claim 10 , wherein forming the conductive lines comprises:
forming second openings in the second dielectric layer, wherein forming the second openings removes the barrier layer to expose top surfaces of the conductive vias; forming a second barrier layer in the second openings; forming a seed layer on the second barrier layer; and forming a second conductive material on the seed layer in the second openings.

16 . The method of claim 10 further comprising:
planarizing the second dielectric layer, the barrier layer, and the conductive vias to expose the top surfaces of the conductive vias, wherein planarizing the second dielectric layer removes the barrier layer to expose top surfaces of the conductive vias;
forming a third dielectric layer over the planarized second dielectric layer, the planarized barrier layer, and the planarized conductive vias;
forming second openings in the third dielectric layer, the top surfaces of the conductive vias being exposed in the second openings; and
forming the conductive lines in the second openings.

17 . The method of claim 10 , wherein the conductive contacts taper from a top surface to a bottom surface, and wherein the conductive vias a same width from a top surface to a bottom surface.

18 . A structure comprising:
a conductive feature on a substrate; a first dielectric layer over the conductive feature and the substrate; a conductive via extending through the first dielectric layer and electrically and physically contacting the conductive feature; a barrier layer being along sidewalls of the conductive via and a bottom surface of the first dielectric layer, the barrier layer being a conformal layer, the barrier layer, conductive via, and first dielectric layer having coplanar top surfaces; a second dielectric layer over the first dielectric layer, the conductive via, and the barrier layer; and a conductive line extending through the second dielectric layer and electrically and physically contacting the conductive via.

19 . The structure of claim 18 further comprising:
a first device on the substrate, the first device comprising a gate electrode on the substrate with source/drain regions on opposing sides of the gate electrode;
a third dielectric layer over the first device and the substrate, the first dielectric layer being over the third dielectric layer; and
conductive contacts in the third dielectric layer and electrically coupled to the gate electrod

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Bo-Jiun
• Lin yu chao
• Lee Tung Ying

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/062

  by smoothing of conductive parts, e.g. by planarisation · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/044

  for electroless plating · CPC title