Thin film transistor, array substrate, and method for fabricating array substrate

Patent metadata

Field	Value
Publication number	US-2023099934-A1
Application number	US-202016978786-A
Country	US
Kind code	A1
Filing date	Jun 22, 2020
Priority date	Jun 11, 2020
Publication date	Mar 30, 2023
Grant date	—

Abstract

A method for fabricating an array substrate, the array substrate, and a thin film transistor are provided. The thin film transistor includes a gate electrode, an active layer, a source electrode, a drain electrode, and an interlayer insulating layer. The active layer is disposed corresponding to the gate electrode. The source electrode and the drain electrode are disposed at both sides of the active layer and electrically connected to the active layer. The interlayer insulating layer is disposed between the active layer and the source electrode, and between the active layer and the drain electrode. The interlayer insulating layer is provided with step-shaped contact holes. The source electrode and the drain electrode are filled in the contact holes and electrically connected to the active layer.

First claim

1 . A thin film transistor, comprising:
a gate electrode; an active layer disposed corresponding to the gate electrode; a source electrode; a drain electrode, wherein the source electrode and the drain electrode are disposed at both sides of the active layer and electrically connected to the active layer; and an interlayer insulating layer disposed between the active layer and the source electrode, and between the active layer and the drain electrode, wherein the interlayer insulating layer is provided with step-shaped contact holes, and the source electrode and the drain electrode are filled in the contact holes and electrically connected to the active layer.

2 . The thin film transistor according to claim 1 , wherein each of the contact holes is composed of a first contact hole and a second contact hole that communicate with each other, the first contact hole is disposed on a side of the second contact hole away from the active layer, a diameter of the first contact hole is greater than that of the second contact hole, the first contact hole has a first smooth curved surface at its end away from the active layer, and the second contact hole has a second smooth curved surface at its end away from the active layer.

3 . The thin film transistor according to claim 1 , wherein the second contact holes extend to the active layer.

4 . The thin film transistor according to claim 3 , further comprising:
a light-shielding layer disposed below the active layer; and a buffer layer disposed between the light-shielding layer and the active layer; wherein the second contact holes extend through the active layer into the buffer layer.

5 . An array substrate, comprising:
a substrate; a first thin film transistor disposed on the substrate and comprising:
a first gate electrode;
a first active layer disposed corresponding to the first gate electrode;
a first source electrode;
a first drain electrode, wherein the first source electrode and the first drain electrode are disposed at both sides of the first active layer and electrically connected to the first active layer; and
a first interlayer insulating layer disposed between the first active layer and the first source electrode, and between the first active layer and the first drain electrode, wherein the first interlayer insulating layer is provided with step-shaped contact holes, and the first source electrode and the first drain electrode are filled in the contact holes and electrically connected to the first active layer; and
a second thin film transistor disposed on the substrate and comprising:
a second gate electrode;
a second active layer disposed corresponding to the second gate electrode and on a side of the first active layer away from the substrate;
a second source electrode;
a second drain electrode, wherein the second source electrode and the second drain electrode are disposed at both sides of the second active layer and electrically connected to the second active layer; and
a second interlayer insulating layer disposed between the second active layer and the second source electrode, and between the second active layer and the second drain electrode;
wherein the first drain electrode and the second source electrode are electrically connected through a first connection metal layer.

6 . The array substrate according to claim 5 , further comprising a light-shielding layer disposed between the substrate and the first thin film transistor, wherein the first source electrode and the light-shielding layer are electrically connected through a second connection metal layer.

7 . The array substrate according to claim 5 , wherein the first active layer is made of low-temperature polysilicon, and the second active layer is made of a metal oxide semiconductor material.

8 . The array substrate according to claim 5 , wherein each of the contact holes is composed of a first contact hole and a second contact hole that communicate with each other, the first contact hole is disposed on a side of the second contact hole away from the first active layer, a diameter of the first contact hole is greater than that of the second contact hole, the first contact hole has a first smooth curved surface at its end away from the first active layer, and the second contact hole has a second smooth curved surface at its end away from the first active layer.

9 . The array substrate according to claim 5 , wherein the second contact holes extend to the first active layer.

10 . The array substrate according to claim 9 , wherein the first thin film transistor further comprises:
a light-shielding layer disposed below the first active layer; and a buffer layer disposed between the light-shielding layer and the first active layer; wherein the second contact holes extend through the first active layer into the buffer layer.

11 . A method for fabricating an array substrate, comprising:
providing a first substrate comprising a substrate, a first active layer, a first interlayer insulating layer, a second active layer, and a second interlayer insulating layer, wherein the first active layer and the second active layer are disposed on the substrate, the second active layer is disposed on a side of the first active layer away from the substrate, the first interlayer insulating layer is disposed between the first active layer and the second active layer, and the second interlayer insulating layer is disposed on the second active layer; coating a photoresist layer on the first substrate; patterning the photoresist layer using a halftone mask, wherein two first through holes are formed at positions of the photoresist layer corresponding to both sides of the first active layer, and two first blind holes are formed at positions of the photoresist layer corresponding to both sides of the second active layer; etching away the second interlayer insulating layer at positions of the first through holes to form first contact holes exposing the first interlayer insulating layer; ashing the patterned photoresist layer, so that the first blind holes form second through holes; etching away the first interlayer insulating layer at positions of the first contact holes to form second contact holes communicating with the first contact holes and exposing the first active layer; etching away the second interlayer insulating layer at positions of the second through holes to form third contact holes exposing the second active layer; removing the photoresist layer; and forming a source/drain metal layer on the second interlayer insulating layer, wherein the source/drain metal layer comprises a first source electrode, a first drain electrode, a second source electrode, a second drain electrode, and a first connection metal layer, the first source electrode and the first drain electrode respectively fill the first contact holes and respectively fill the second contact holes communicating with the first contact holes, the second source electrode and the second drain electrode respectively fill the third contact holes, and the first drain electrode and the second source electrode are electrically connected through the first connection metal layer.

12 . The method for fabricating the array substrate according to claim 11 , wherein the second contact holes extend from the first interlayer insulating layer to the active layer.

13 . The method for fabricating the array substrate according to claim 11 , wherein:
the first substrate further comprises a first gate metal layer and a first light-shielding layer that are disposed on the substrate, the first gate metal layer is disposed corresponding to the first active layer, the first light

Assignees

• Wuhan China Star Optoelectronics Semiconductor Display Tech Co Ltd

Inventors

• Gong Jixiang
• Zhang Yixian
• Xianyu Wenxu

Classifications

• H10D86/423 Primary

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D30/6729

  characterised by the electrodes · CPC title

• H10D30/6723

  having light shields · CPC title