Liquid crystal display

Patent metadata

Field	Value
Publication number	US-2020292897-A1
Application number	US-202016816074-A
Country	US
Kind code	A1
Filing date	Mar 11, 2020
Priority date	Mar 14, 2019
Publication date	Sep 17, 2020
Grant date	—

Abstract

A liquid crystal display includes: an active matrix substrate; an opposite substrate facing the active matrix substrate; and a liquid crystal layer provided between the active matrix substrate and the opposite substrate. The liquid crystal display includes a plurality of pixels. The active matrix substrate includes: a first substrate; a base coat layer; a plurality of TFTs; a plurality of scanning wirings; and a plurality of signal wirings. The active matrix substrate further includes a plurality of second light-shielding layers provided between the first substrate and the base coat layer. The base coat layer includes a silicon nitride layer.

First claim

What is claimed is:

1 . A liquid crystal display comprising:
an active matrix substrate; an opposite substrate facing the active matrix substrate; and a liquid crystal layer provided between the active matrix substrate and the opposite substrate, the liquid crystal display comprising: a plurality of pixels arranged in a matrix with a plurality of rows and a plurality of columns, wherein the active matrix substrate includes: a first substrate; a base coat layer provided on the first substrate; a plurality of TFTs provided on the base coat layer and each disposed in each of the plurality of pixels; a plurality of scanning wirings extending in the row direction; and a plurality of signal wirings extending in the column direction, the opposite substrate includes: a second substrate; and a plurality of first light-shielding layers provided on the second substrate and each extending in the column direction, the plurality of first light-shielding layers each overlap with any of the plurality of signal wirings when viewed from a direction of a normal line of the display surface, the plurality of TFTs each includes: a crystalline silicon semiconductor layer including a channel region; a gate insulating layer covering the crystalline silicon semiconductor layer; a gate electrode provided on the gate insulating layer; a source electrode including a first connection portion being in contact with the crystalline silicon semiconductor layer; and a drain electrode including a second connection portion being in contact with the crystalline silicon semiconductor layer, the active matrix substrate further includes a plurality of second light-shielding layers provided between the first substrate and the base coat layer, the plurality of second light-shielding layers are each integrally formed so as to overlap with the channel region, at least a part of the first connection portion, and the second connection portion of at least one of the plurality of TFTs when viewed from a direction of a normal line of the display surface, and the base coat layer includes a silicon nitride layer.

2 . The liquid crystal display according to claim 1 , wherein
the base coat layer further includes a silicon oxide layer provided on the silicon nitride layer.

3 . The liquid crystal display according to claim 2 , wherein
the active matrix substrate further includes an interlayer insulating layer covering the gate insulating layer and the gate electrode; and the interlayer insulating layer has a thickness t 1 , the gate insulating layer has a thickness t 2 , and the silicon oxide layer has a thickness t 3 , where a relationship represented by t 3 >(t 1 +t 2 )×0.3 is satisfied.

4 . The liquid crystal display according to claim 2 , wherein
the active matrix substrate further includes an interlayer insulating layer covering the gate insulating layer and the gate electrode; and the interlayer insulating layer has a thickness t 1 , the gate insulating layer has a thickness t 2 , and the silicon oxide layer has a thickness t 3 , where a relationship represented by t 3 >(t 1 +t 2 )×0.5 is satisfied.

5 . The liquid crystal display according to claim 2 , wherein
the silicon nitride layer has a thickness t 4 of larger than 30 nm.

6 . The liquid crystal display according to claim 2 , wherein
the silicon nitride layer has a thickness t 4 of larger than 50 nm.

7 . The liquid crystal display according to claim 2 , wherein
the first connection portion of the source electrode and the second connection portion of the drain electrode pass through the crystalline silicon semiconductor layer and the silicon oxide layer and are in contact with the silicon nitride layer.

8 . The liquid crystal display according to claim 1 , wherein
the base coat layer substantially includes only the silicon nitride layer.

9 . The liquid crystal display according to claim 8 , wherein
the interlayer insulating layer has a thickness t 1 , the gate insulating layer has a thickness t 2 , and the silicon nitride layer has a thickness t 4 a in a region overlapping with the channel region, where a relationship represented by t 4 a >(t 1 +t 2 )×0.3 is satisfied.

10 . The liquid crystal display according to claim 8 , wherein
the interlayer insulating layer has a thickness t 1 , the gate insulating layer has a thickness t 2 , and the silicon nitride layer has a thickness t 4 a in a region overlapping with the channel region, where a relationship represented by t 4 a >(t 1 +t 2 )×0.5 is satisfied.

11 . The liquid crystal display according to claim 8 , wherein
the silicon nitride layer has a thickness t 4 b of larger than 30 nm in a region overlapping with the first connection portion or the second connection portion.

12 . The liquid crystal display according to claim 8 , wherein
the silicon nitride layer has a thickness t 4 b of larger than 50 nm in a region overlapping with the first connection portion or the second connection portion.

13 . The liquid crystal display according to claim 1 , wherein
the crystalline silicon semiconductor layer is a polycrystalline silicon semiconductor layer.

14 . The liquid crystal display according to claim 1 , wherein
the plurality of second light-shielding layers are each integrally formed so as to overlap with the channel region, at least a part of the first connection portion, and at least a part of the second connection portion of two or more of the plurality of TFTs when viewed from a direction of a normal line of the display surface.

Assignees

• Sharp Kk

Inventors

• Aichi Hiroshi

Classifications

• G02F1/13685

  Top gates · CPC title

• G02F1/136209 Primary

  Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element · CPC title

• G02F1/133512

  Light shielding layers, e.g. black matrix (G02F1/136209 takes precedence) · CPC title

• G02F1/136286 Primary

  Wiring, e.g. gate line, drain line · CPC title

• G02F1/136277

  formed on a semiconductor substrate, e.g. of silicon · CPC title