Thin film transistor, manufacturing method thereof, and display panel

Patent metadata

Field	Value
Publication number	US-2021376160-A1
Application number	US-202016770827-A
Country	US
Kind code	A1
Filing date	Jun 5, 2020
Priority date	May 26, 2020
Publication date	Dec 2, 2021
Grant date	—

Abstract

A thin film transistor is provided. The thin film transistor includes an active layer, and the active layer includes a plurality of stacked structures, and each of the stacked structures includes: a N-layer indium oxidation layer; a gallium oxidation layer, the gallium oxidation layer is provided on the indium oxidation layer of the N-layer indium oxidation layer; and a zinc oxidation layer is provided on the gallium oxidation layer. These stacked structures improve the performance of the thin film transistor. A preparation method of the thin film transistor and a display panel containing the thin film transistor is also provided.

First claim

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7 . A method of manufacturing a thin film transistor, comprising:
step S 01 , manufacturing a substrate; step S 02 , manufacturing a light-shielding layer on the substrate; step S 03 , manufacturing a buffer layer on the substrate, and the buffer layer covering the light-shielding layer; step S 1 , manufacturing an active layer comprising a plurality of stacked structures on the buffer layer by an atomic layer deposition method, comprising: step S 11 , using the buffer layer as a current layer; step S 12 , using the atomic layer deposition method, sequentially depositing N-layers of indium oxide on the current layer, depositing the gallium oxidation layer on the N-layers of indium oxide, and depositing the zinc oxidation layer on the gallium oxidation layer to form the stacked structure, wherein N is an integer greater than 1; step S 13 , using the zinc oxidation layer on the currently formed stacked structure as the current layer, and repeatedly performing the step S 12 until several stacked structures are formed; and step S 14 , patterning the plurality of the stacked structures to obtain the active layer; wherein the deposition rates of the zinc oxidation layer, the gallium oxidation layer and the N-layers of indium oxide are sequentially reduced.

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10 . The method of manufacturing the thin film transistor as claimed in claim 7 , wherein after the step S 1 further comprises the following steps:
s 21 , manufacturing a gate insulating layer on the active layer;
s 22 , manufacturing a gate layer on the gate insulating layer;
s 23 , manufacturing an interlayer dielectric layer on the buffer layer and covering the gate layer, the gate insulating layer, and the active layer;
s 24 , manufacturing a source-drain layer on the interlayer dielectric layer, and the source-drain layer comprises at least one of source electrodes and at least one of drain electrodes arranged at intervals;
s 25 , manufacturing a passivation layer on the interlayer dielectric layer and covering source-drain layer; and
s 26 , manufacturing a pixel electrode layer on the passivation layer.

11 . The method of manufacturing the thin film transistor as claimed in claim 10 , further comprising:
manufacturing a first via hole on the interlayer dielectric layer and the buffer layer is configured to electrically connect the source electrode and the light-shielding layer; manufacturing a second via hole on the interlayer dielectric layer for electrically connecting the source electrode and the active layer; manufacturing a third via hole on the interlayer dielectric layer for electrically connecting the drain electrode and the active layer; and manufacturing a fourth via hole on the passivation layer and configured to electrically connect the drain electrode and the pixel electrode layer.

12 . The method of manufacturing the thin film transistor as claimed in claim 7 , wherein thicknesses of the indium oxidation layer, the gallium oxidation layer, and the zinc oxidation layer ranges from 50 A to 300 A.

13 . The method of manufacturing the thin film transistor as claimed in claim 7 , wherein deposition rates of the indium oxidation layer, the gallium oxidation layer, and the zinc oxidation layer ranges from 0.8 A/cycle to 2.2 A/cycle

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Assignees

• Shenzhen China Star Optoelectronics Semiconductor Display Tech Co Ltd

Inventors

• Luo Chuanbao

Classifications

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/021

  of multiple TFTs · CPC title

• H10D30/6755 Primary

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title