Display apparatus
US-2024414942-A1 · Dec 12, 2024 · US
US10192891B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10192891-B2 |
| Application number | US-201715459634-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 15, 2017 |
| Priority date | Mar 16, 2016 |
| Publication date | Jan 29, 2019 |
| Grant date | Jan 29, 2019 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
According to one embodiment, a thin film transistor includes an oxide semiconductor layer provided above an insulating substrate and including a channel region between a source region and a drain region, a first insulating film provided in a region on the oxide semiconductor layer, which corresponds to the channel region, a gate electrode provided on the first insulating film, a first protective film provided on the oxide semiconductor layer, the first insulating film and the gate electrode, as an insulating film containing a metal, a second protective film provided on the first protective film and a third protective film provided on the second protective film, as an insulating film containing a metal.
Opening claim text (preview).
What is claimed is: 1. A thin film transistor comprising: an oxide semiconductor layer provided above an insulating substrate and including a source region, a drain region and a channel region between the source region and the drain region; a first insulating film provided in a region on the oxide semiconductor layer, which corresponds to the channel region; a gate electrode provided on the first insulating film; a first protective film provided on the oxide semiconductor layer, the first insulating film and the gate electrode, as an insulating film containing a metal; a second protective film provided on the first protective film; and a third protective film provided on the second protective film, as an insulating film containing a metal, wherein the first protective film directly contacts sidewalls and a top surface of the gate electrode, wherein the third protective film is thicker than the first protective film. 2. The thin film transistors of claim 1 , wherein the first protective film and the third protective film are each formed of aluminum oxide. 3. The thin film transistor of claim 1 , wherein the second protective film is formed of at least one of silicon oxide, silicon nitride or silicon oxynitride. 4. A display device comprising the thin film transistor of claim 1 . 5. The display device of claim 4 , comprising an organic electroluminescence element. 6. The display device of claim 4 , comprising a liquid crystal layer. 7. The thin film transistor of claim 1 , wherein a top surface of the third protective film over the source region is closer to a top surface of the insulating substrate than a top surface of the third protective film over the gate electrode.
in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title
Active matrix addressed cells {(G02F1/134336, G02F1/134363 take precedence)} · CPC title
comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title
Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title
Electricity · mapped topic
Related publications grouped by family.
Answers are generated from the same data shown on this page.