Integrated Assemblies, and Methods of Forming Integrated Assemblies

Patent metadata

Field	Value
Publication number	US-2023065142-A1
Application number	US-202217968651-A
Country	US
Kind code	A1
Filing date	Oct 18, 2022
Priority date	Aug 27, 2020
Publication date	Mar 2, 2023
Grant date	—

Abstract

Some embodiments include an integrated assembly having a pair of adjacent memory-block-regions, and having a separator structure between the adjacent memory-block-regions. The memory-block-regions include a first stack of alternating conductive levels and first insulative levels. The separator structure includes a second stack of alternating second and third insulative levels. The second insulative levels are substantially horizontally aligned with the conductive levels, and the third insulative levels are substantially horizontally aligned with the first insulative levels. Some embodiments include methods of forming integrated assemblies.

First claim

I/We claim:

1 . A method of forming an integrated assembly, comprising:
forming a first stack of alternating first and second materials over a source structure; the second material being an insulative material; a region of the first stack being a memory array region and having a first memory-block-region laterally adjacent a second memory-block-region; forming a first array of cell-pillar-openings within the first memory-block-region, a second array of the cell-pillar-openings within the second memory-block-region, and a linear string of the cell-material-openings within a separator-structure-region between the first and second memory-block-regions; the cell-pillar-openings extending through the first stack; the linear string extending along a first direction; protecting interior regions of the cell-pillar-openings within the first and second arrays with sacrificial material while leaving interior regions of the cell-pillar-openings of the linear string exposed; recessing the first material from the exposed interior regions of the cell-pillar-openings of the linear string to merge the cell-pillar-openings of the linear string with one another along the first direction; removing the sacrificial material; forming cell materials within the cell-pillar-openings of the first and second arrays, and within the merged cell-pillar-openings of the linear string; the cell materials within the merged cell-pillar-openings being incorporated into a separator structure; the separator structure comprising a second stack which comprises alternating first and second insulative levels; the second insulative levels comprising the second material; forming a first slit on an opposing side of the first memory-block-region from the separator structure, and forming a second slit on an opposing side of the second memory-block-region from the separator structure; removing the first material with etchant flowed into the first and second slits to form voids; forming conductive material within the voids; and forming panels within the first and second slits.

2 . The method of claim 1 wherein the first stack comprises two or more decks stacked one atop another, and wherein first regions of the cell-pillar-openings are first formed in a lower of the decks, and then an upper of the decks is formed and second regions of the cell-pillar-opening are formed in the upper of the decks.

3 . The method of claim 1 wherein the cell materials include channel material, tunneling material, charge-trapping material and charge-blocking material; and wherein the channel material is configured as channel-material-pillars.

4 . The method of claim 3 wherein the separator structure includes one or both of the charge-blocking material and the charge-trapping material.

5 . The method of claim 4 wherein the charge-blocking material comprises silicon dioxide, and wherein the charge-trapping material comprises silicon nitride.

6 . The method of claim 3 wherein the first insulative levels comprise one or more of the cell materials.

7 . The method of claim 1 further comprising:
forming a third stack over the first and second stacks after forming the cell materials, wherein the third stack comprises the alternating first and second materials;
forming upper channel structures extending through the third stack to the channel-material-pillars within the first and second memory-block-regions;
forming the slits to extend through the third stack; and
replacing the first material of the third stack with the conductive material to form conductive levels within the third stack.

8 . The method of claim 7 wherein the first conductive levels of the third stack are SGD levels and extend to an SGD staircase region, and wherein the separator structure extends through the SGD staircase region.

9 . A method of forming an integrated assembly, comprising:
forming a pair of adjacent memory-block-regions, the memory-block-regions comprising a first stack of alternating conductive levels and first insulative levels; and forming a separator structure between the adjacent memory-block-regions, said separator structure comprising a second stack of alternating second and third insulative levels, the second insulative levels being substantially horizontally aligned with the conductive levels, and the third insulative levels being substantially horizontally aligned with the first insulative levels, the separator structure extending along a first direction and having a first region offset from a second region along the first direction, the first region comprising the second stack and the second region not comprising the second stack.

10 . The method of claim 9 comprising:
forming a conductive source structure under the memory-block-regions and under the separator structure;
forming first channel-material-pillars within the memory-block-regions and extending through the first stack to electrically couple with the source structure; and
forming second channel-material-pillars within the separator structure and extending through the second stack.

11 . The method of claim 10 wherein:
the first channel-material-pillars are along a first pitch along the first direction;
the second channel-material-pillars are along a second pitch along the first direction; and
the second pitch is greater than the first pitch.

12 . The method of claim 9 wherein the first and second regions have widths along a second direction orthogonal to the first direction, and wherein the second region is at least about 150% wider than the first region.

13 . The method of claim 9 wherein the second region comprises an insulative panel extending through the first stack.

14 . The method of claim 9 further comprising forming an SGD stack over the first stack and second stack, a first region of the separator structure being between the first and second memory-block-regions under the SGD stack.

15 . The method of claim 9 wherein the memory-block-regions are within a memory array region, wherein an SGD staircase region formed laterally offset from the memory array region, with said SGD staircase region including the SGD stack over the first stack; and wherein the separator structure has a second region which extends through the first stack in the SGD staircase region.

16 . The method of claim 9 wherein the first stack includes at least two decks stacked one atop another.

Assignees

• Micron Technology Inc

Inventors

• Fukuzumi Yoshiaki
• Tessariol Paolo
• Wells David H
• Heineck Lars P
• Hill Richard J
• Xu Lifang
• Chary Indra V
• Camerlenghi Emilio

Classifications

• H10W95/00

  Packaging processes not covered by the other groups of this subclass · CPC title

• H10W90/00

  Package configurations · CPC title

• H10B43/10 Primary

  characterised by the top-view layout · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title