Three-dimensional memory device having an epitaxial vertical semiconductor channel and method for making the same

Patent metadata

Field	Value
Publication number	US-2020335516-A1
Application number	US-202016917597-A
Country	US
Kind code	A1
Filing date	Jun 30, 2020
Priority date	Mar 1, 2019
Publication date	Oct 22, 2020
Grant date	—

Abstract

A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a first single crystalline semiconductor layer, and memory stack structures extending through the alternating stack and containing respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die includes a peripheral circuitry.

First claim

What is claimed is:

1 . A method of forming a semiconductor structure, comprising:
forming a source-level sacrificial layer on a first single crystalline semiconductor layer; forming an alternating stack of insulating layers and sacrificial material layers over the source-level sacrificial layer; forming memory openings through the alternating stack; forming in-process memory opening fill structures in the memory openings, wherein each of the in-process memory opening fill structures comprises a memory film and a sacrificial fill pillar; forming a source cavity by removing the source-level sacrificial layer selective to the alternating stack and the first single crystalline semiconductor layer; forming a single crystalline semiconductor source layer by selectively growing a doped semiconductor material in the source cavity; replacing the sacrificial material layers with electrically conductive layers; forming memory cavities by removing the sacrificial fill pillars selective to the memory films; and forming single crystalline vertical semiconductor channels by selectively growing a single crystalline semiconductor channel material in the memory cavities.

2 . The method of claim 1 , further comprising:
providing a first single crystalline semiconductor substrate; forming a hydrogen implanted layer in the first single crystalline semiconductor substrate, wherein the first single crystalline semiconductor substrate is divided into the first single crystalline semiconductor layer and an additional single crystalline semiconductor layer; and cleaving off the additional single crystalline semiconductor layer from the first single crystalline semiconductor layer prior to forming the source-level sacrificial layer.

3 . The method of claim 2 , further comprising:
providing a carrier substrate; forming a plurality of grooves in a front surface of the carrier substrate; forming a sacrificial cover layer over the plurality of grooves by anisotropically depositing a sacrificial cover material, wherein laterally-extending cavities encapsulated by the sacrificial cover layer and the carrier substrate are formed in the plurality of grooves; and attaching the first single crystalline semiconductor substrate over the sacrificial cover layer after formation of the hydrogen implanted layer, wherein the additional single crystalline semiconductor layer is cleaved off the first single crystalline semiconductor layer after attaching the first single crystalline semiconductor substrate over the sacrificial cover layer.

4 . The method of claim 3 , further comprising:
forming a silicon oxide layer on the first single crystalline semiconductor substrate, wherein the hydrogen implanted layer is formed by implanting hydrogen through the silicon oxide layer; forming a silicate glass capping layer over the sacrificial cover layer; and bonding the silicon oxide layer to the silicate glass capping layer.

5 . The method of claim 3 , further comprising detaching the carrier substrate from an assembly comprising the first single crystalline semiconductor layer, the single crystalline semiconductor source layer, the insulating layers, the electrically conductive layers, and the single crystalline vertical semiconductor channels by flowing an etchant that selectively etches a material of the sacrificial cover layer into the plurality of grooves.

6 . The method of claim 1 , further comprising:
forming a backside trench through the alternating stack, wherein a surface of the source-level sacrificial layer is physically exposed at a bottom of the backside trench; and providing an etchant that selectively etches a material of the source-level sacrificial layer selective to materials of the insulating layers and the spacer material layers.

7 . The method of claim 1 , wherein:
the source cavity is vertically bounded by a bottom surface of a bottommost one of the insulating layers and by a top surface of the first single crystalline semiconductor layer; and the doped semiconductor material grows upward from the top surface of the first single crystalline semiconductor layer to the bottom surface of the bottommost one of the insulating layers during formation of the single crystalline source layer.

8 . The method of claim 1 , wherein:
the memory films are physically exposed to the source cavity after formation of the source cavity; and the method further comprises physically exposing the sacrificial fill pillars by isotropically etching physically exposed portions of the memory films.

9 . The method of claim 1 , wherein:
cylindrical sidewalls of the single crystalline semiconductor source layer are physically exposed around the memory cavities; the single crystalline vertical semiconductor channels are epitaxially aligned to a single crystalline semiconductor material of the single crystalline semiconductor source layer across cylindrical interfaces located at bottom portions of the memory openings; and the method further comprises forming drain regions at upper ends of the single crystalline vertical semiconductor channels.

10 . The method of claim 1 , further comprising:
forming first dielectric material layers embedding first metal interconnect structures and first bonding pads over the insulating layers and the electrically conductive layers; forming logic devices on a second single crystalline semiconductor layer; forming second dielectric material layers embedding second metal interconnect structures and second bonding pads over the second semiconductor devices; and bonding the second bonding pads to the first bonding pads, wherein the first metal interconnect structures, the second metal interconnect structures, the first bonding pads, and the second bonding pads provide electrically conductive paths between the logic devices and memory devices located over the first single crystalline semiconductor layer.

11 . A method of forming a semiconductor structure, comprising:
forming a silicon oxide layer over a top surface of a single crystalline semiconductor substrate; forming a hydrogen implanted layer within the single crystalline semiconductor substrate by implanting hydrogen atoms through the silicon oxide layer, wherein the single crystalline semiconductor substrate is divided into a proximal single crystalline semiconductor layer contacting the silicon oxide layer and a distal single crystalline semiconductor layer that is spaced from the silicon oxide layer by the proximal single crystalline semiconductor layer; attaching a handle substrate to the silicon oxide layer; detaching the distal single crystalline semiconductor layer from an assembly of the proximal single crystalline semiconductor layer, the silicon oxide layer, and the handle substrate by cleaving the single crystalline semiconductor substrate at the hydrogen implanted layer; forming semiconductor devices on a physically exposed horizontal surface of the proximal single crystalline semiconductor layer; and forming dielectric material layers embedding metal interconnect structures and bonding pads over the semiconductor devices.

12 . The method of claim 11 , further comprising forming semiconductor dies by dicing a composite structure comprising the dielectric material layers, the semiconductor devices, the proximal single crystalline semiconductor layer, the silicon oxide layer, and the handle substrate into a plurality of semiconductor dies.

13 . The method of claim 12 , further comprising:
forming additional semiconductor devices on an additional single crystalline semiconductor layer; forming additional dielectric material layers embedding additi

Assignees

• Sandisk Technologies Llc

Inventors

• RAJASHEKHAR Adarsh
• Makala Raghuveer S
• Zhou Fei

Classifications

• H01L27/11519

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic

• H01L27/11524

  Electricity · mapped topic

• H01L27/11543

  Electricity · mapped topic