Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-2019198523-A1
Application number	US-201816120412-A
Country	US
Kind code	A1
Filing date	Sep 3, 2018
Priority date	Dec 27, 2017
Publication date	Jun 27, 2019
Grant date	—

Abstract

A semiconductor memory device includes first and second wiring layers above a semiconductor substrate, a memory pillar extending through the first and second wiring layers, a first plug contacting the first wiring layer, a second plug contacting the second wiring layer, a first pillar adjacent to the first plug and extending through the first wiring layer, and a second pillar adjacent to the second plug and extending through the first and second wiring layers. The memory pillar includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, and a third insulating layer, a charge storage layer, and a fourth insulating layer on a side surface of the second semiconductor layer. The distance between the center of the first plug and the center of the first pillar is greater than the distance between the center of the second plug and the center of the second pillar.

First claim

What is claimed is:

1 . A semiconductor memory device comprising:
a first wiring layer above a semiconductor substrate and a first insulating layer therebetween; a second wiring layer above the first wiring layer and a second insulating layer therebetween; a memory pillar extending in a first direction intersecting the semiconductor substrate and through the first and second wiring layers, the memory pillar comprising a first semiconductor layer, a second semiconductor layer located over the first semiconductor layer, and a third insulating layer, a charge storage layer, and a fourth insulating layer located on a side surface of the second semiconductor layer; a first plug contacting and electrically connected to the first wiring layer; a second plug contacting and electrically connected to the second wiring layer; a first pillar located adjacent to the first plug and extending through the first wiring layer; and a second pillar located adjacent to the second plug and extending through the first and second wiring layers, wherein the first wiring layer is a lowermost wiring layer above the semiconductor substrate, and wherein the distance between the center of the first plug and the center of the first pillar is greater than the distance between the center of the second plug and the center of the second pillar.

2 . The semiconductor memory device according to claim 1 ,
wherein the first insulating layer is located on the semiconductor substrate, the memory pillar is electrically connected to the semiconductor substrate, and the first and second pillars contact the semiconductor substrate.

3 . The semiconductor memory device according to claim 1 ,
wherein each of the first and second pillars includes a third semiconductor layer, a fourth semiconductor layer located over the third semiconductor layer, and a fifth insulating layer, a charge storage layer, and a sixth insulating layer located on a side surface of the fourth semiconductor layer.

4 . The semiconductor memory device according to claim 1 ,
wherein the first and second pillars are in an electrically floating state.

5 . The semiconductor memory device according to claim 1 ,
wherein the first wiring layer includes a first terrace at which the first plug is connected to the first wiring layer; the second wiring layer includes a second terrace at which the second plug is connected to the second wiring layer; and the second terrace terminates inwardly of the first terrace in a second direction parallel to the semiconductor substrate.

6 . The semiconductor memory device according to claim 1 , further comprising:
a bit line connected to the memory pillar; a sense amplifier connected to the memory pillar through the bit line; and a row decoder connected to the first and second plugs.

7 . The semiconductor memory device according to claim 1 ,
wherein the distance between the upper surface of the first semiconductor layer and the semiconductor substrate is greater than the distance between the upper surface of the first wiring layer and the semiconductor substrate, and less than of the distance between the bottom surface of the second wiring layer and the semiconductor substrate.

8 . The semiconductor memory device according to claim 1 , further comprising a plurality of word lines spaced from one another in the first direction and extending in a second direction crossing the first direction; and
adjacent ones of the word lines in the first direction are connected to contacts adjacent to one another in the second direction.

9 . The semiconductor memory device according to claim 1 , further comprising a plurality of word lines spaced from one another in the first direction and extending in a second direction crossing the first direction; and
adjacent ones of the word lines in the first direction are connected to contacts adjacent to one another in one of the second direction and a third direction crossing the first and the second directions.

10 . The semiconductor memory device according to claim 9 , further comprising a source line extending between adjacent ones of the word lines in the third direction.

11 . A semiconductor memory device comprising:
a first wiring layer above a semiconductor substrate and a first insulating layer therebetween; a second wiring layer above the first wiring layer and a second insulating layer therebetween; a memory pillar extending in a first direction intersecting the semiconductor substrate and through the first and second wiring layers, the memory pillar comprising a first semiconductor layer, a second semiconductor layer located over the first semiconductor layer, and a third insulating layer, a charge storage layer, and a fourth insulating layer located on a side surface of the second semiconductor layer; a first plug contacting and electrically connected to the first wiring layer; a second plug contacting and electrically connected to the second wiring layer; a first pillar located adjacent to the first plug and extending through the first wiring layer; and a second pillar located adjacent to the second plug and extending through the first and second wiring layers, the second pillar spaced from the first pillar in a second direction crossing the first direction, wherein the first wiring layer is a lowermost wiring layer above the semiconductor substrate and extends, in the second direction, outwardly of the second wiring layer, and wherein the distance between the center of the first plug and the center of the first pillar is greater than the distance between the center of the second plug and the center of the second pillar.

12 . The semiconductor memory device according to claim 11 ,
wherein the first insulating layer is located on the semiconductor substrate, the memory pillar is electrically connected to the semiconductor substrate, and the first and second pillars contact the semiconductor substrate.

13 . The semiconductor memory device according to claim 11 ,
wherein each of the first and second pillars includes a third semiconductor layer, a fourth semiconductor layer located over the third semiconductor layer, and a fifth insulating layer, a charge storage layer, and a sixth insulating layer located on a side surface of the fourth semiconductor layer.

14 . The semiconductor memory device according to claim 11 ,
wherein the first and second pillars are in an electrically floating state.

15 . The semiconductor memory device according to claim 11 ,
wherein the first wiring layer includes a first terrace at which the first plug is connected to the first wiring layer; the second wiring layer includes a second terrace at which the second plug is connected to the second wiring layer; and the second terrace terminates inwardly of the first terrace in a second direction parallel to the semiconductor substrate.

16 . The semiconductor memory device according to claim 11 , further comprising:
a bit line connected to the memory pillar; a sense amplifier connected to the memory pillar through the bit line; and a row decoder connected to the first and second plugs.

17 . The semiconductor memory device according to claim 11 ,
wherein the distance between the upper surface of the first semiconductor layer and the semiconductor substrate is greater than the distance between the upper surface of the first wiring layer and the semiconductor substrate, and less than of the distance between the bottom surface of the second wiring layer and the semiconductor substrate.

18 . The se

Assignees

• Toshiba Memory Corp

Inventors

• Nakanishi Yusuke
• Yamanaka Takaya
• Matsumura Akira

Classifications

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• H01L27/1157

  Electricity · mapped topic