Packaged electronic devices having dielectric substrates with thermally conductive adhesive layers

Patent metadata

Field	Value
Publication number	US-2022238426-A1
Application number	US-202117159925-A
Country	US
Kind code	A1
Filing date	Jan 27, 2021
Priority date	Jan 27, 2021
Publication date	Jul 28, 2022
Grant date	—

Abstract

A packaged electronic device comprises a power semiconductor die that comprises a first terminal and a second terminal, a lead frame comprising a lower side and an upper side that comprises a die pad region, a first lead and a second lead, wherein the first lead is integral with the lead frame and electrically connected to the first terminal of the power semiconductor die through the lead frame, a dielectric substrate, and a thermally conductive adhesion layer on an upper side of the dielectric substrate. The power semiconductor die is on the die pad region of the lead frame and the lead frame is on an upper side of the thermally conductive adhesion layer

First claim

1 . A packaged electronic device, comprising:
a power semiconductor die that comprises a first terminal and a second terminal; a lead frame comprising a lower side and an upper side that comprises a die pad region; a first lead and a second lead; a dielectric substrate; and a thermally conductive adhesion layer on an upper side of the dielectric substrate, wherein the power semiconductor die is on the die pad region of the lead frame and the lead frame is on an upper side of the thermally conductive adhesion layer.

2 . The packaged electronic device of claim 30 , wherein the dielectric substrate comprises a ceramic substrate and the thermally conductive adhesion layer comprises a metal braze layer.

3 . The packaged electronic device of claim 2 , wherein the metal braze layer is directly attached to the ceramic substrate and to the lower side of the lead frame.

4 - 5 . (canceled)

6 . The packaged electronic device of claim 2 , further comprising an overmold package that encapsulates an upper side and side surfaces of the power semiconductor die.

7 . The packaged electronic device of claim 2 , further comprising a lower metal cladding layer on a lower side of the dielectric substrate.

8 . The packaged electronic device of claim 7 , wherein the lead frame and the lower metal cladding layer are formed of the same metal.

9 . The packaged electronic device of claim 8 , wherein the metal braze layer is a first metal braze layer, and wherein a second metal braze layer is between an upper side of the lower metal cladding layer and the lower side of the dielectric substrate.

10 . (canceled)

11 . The packaged electronic device of claim 2 , further comprising an upper metal cladding layer on an upper side of the metal braze layer and a substrate attach metal layer that is interposed between the upper metal cladding layer and the lead frame.

12 . A packaged electronic device, comprising:
a dielectric substrate; a first metal cladding layer on a lower side of the dielectric substrate; a lead frame that has an upper side that comprises a die pad region and a lower side that is on the upper side of the dielectric substrate; a power semiconductor die that is on the die pad region of the lead frame.

13 . The packaged electronic device of claim 12 , further comprising an overmold encapsulation that encapsulates an upper side and side surfaces of the power semiconductor die and at least an upper side of the dielectric substrate.

14 . The packaged electronic device of claim 13 , wherein the dielectric substrate comprises a ceramic substrate.

15 . The packaged electronic device of claim 14 , further comprising a first metal braze layer between the first metal cladding layer and the ceramic substrate.

16 . The packaged electronic device of claim 15 , further comprising a second metal braze layer on the upper side of the ceramic substrate.

17 . The packaged electronic device of claim 16 , wherein the second metal braze layer is directly attached to both the upper side of the ceramic substrate and to the lower side of the lead frame.

18 . (canceled)

19 . The packaged electronic device of claim 12 , wherein the lead frame further comprises a first lead that is integral with and electrically connected to the die pad region.

20 . (canceled)

21 . A packaged electronic device, comprising:
a dielectric substrate; a first metal cladding layer on a lower side of the dielectric substrate; a power semiconductor die that is mounted on an upper side of the dielectric substrate; an overmold encapsulation that surrounds an upper side and side surfaces of the power semiconductor die and at least partially surrounds sidewalls of the dielectric substrate while exposing at least a portion of the first metal cladding layer; and a first lead and a second lead that each extend through the overmold encapsulation and that are electrically connected to the power semiconductor die, wherein the power semiconductor die is electrically isolated from the first metal cladding layer.

22 . The packaged electronic device of claim 21 , wherein the dielectric substrate comprises a ceramic substrate and a first metal braze layer is on an upper side of the ceramic substrate.

23 . The packaged electronic device of claim 22 , further comprising a lead frame that comprises an upper side comprising a die pad region, wherein a lower side of the lead frame is mounted on an upper side of the first metal braze layer and the power semiconductor die is mounted on the die pad region.

24 . The packaged electronic device of claim 23 , wherein the first metal braze layer is directly attached to the ceramic substrate and to the lower side of the lead frame.

25 . The packaged electronic device of claim 24 , wherein the first lead is integral with the lead frame and is electrically connected to a first terminal of the power semiconductor die.

26 - 27 . (canceled)

28 . The packaged electronic device of claim 23 , further comprising an upper metal cladding layer on an upper side of the first metal braze layer and a substrate attach metal layer that is interposed between the upper metal cladding layer and the lead frame.

29 . (canceled)

30 . The packaged electronic device of claim 1 , wherein the first lead is integral with the lead frame and electrically connected to the first terminal of the power semiconductor die through the lead frame.

31 . (canceled)

Assignees

• Cree Inc

Inventors

• Seal Sayan
• Saxena Kuldeep
• Balaraman Devarajan

Classifications

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title

• H10W70/479

  on or in insulating or insulated package substrates, interposers, or redistribution layers · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title