Molded package with chip carrier comprising brazed electrically conductive layers

Patent metadata

Field	Value
Publication number	US-10074590-B1
Application number	US-201715649459-A
Country	US
Kind code	B1
Filing date	Jul 13, 2017
Priority date	Jul 2, 2017
Publication date	Sep 11, 2018
Grant date	Sep 11, 2018

Abstract

A package which comprises a chip carrier, at least one electronic chip mounted on the chip carrier, an electrically conductive contact structure electrically coupled with the at least one electronic chip, and a mold-type encapsulant encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip, wherein the chip carrier comprises a thermally conductive and electrically insulating core covered on both opposing main surfaces thereof by a respective brazed electrically conductive layer.

First claim

What is claimed is:

1. A package, comprising:
a chip carrier;
at least one electronic chip mounted on the chip carrier;
an electrically conductive contact structure electrically coupled with the at least one electronic chip;
a mold-type encapsulant encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip;
wherein the chip carrier comprises a thermally conductive and electrically insulating core covered on both opposing main surfaces thereof at least partially by a respective brazed electrically conductive layer.

2. The package according to claim 1 , wherein at least one of the electrically conductive layers has a larger thickness than a thickness of the thermally conductive and electrically insulating core.

3. The package according to claim 1 , wherein at least one of the electrically conductive layers has a thickness of more than 0.4 mm, in particular more than 0.5 mm, more particularly more than 0.6 mm.

4. The package according to claim 1 , wherein at least one of the electrically conductive layers is a metal layer, in particular a copper layer or an alloy comprising copper.

5. The package according to claim 1 , wherein the thermally conductive and electrically insulating core is a ceramic core, in particular comprises or consists of one of the group consisting of silicon nitride, aluminium nitride, and aluminium oxide.

6. The package according to claim 1 , comprising a brazing structure, in particular comprising or consisting of silver, between the thermally conductive and electrically insulating core and the electrically conductive layers.

7. The package according to claim 1 , wherein the chip carrier is an Active Metal Brazed (AMB) substrate.

8. The package according to claim 1 , wherein at least part of a surface of the chip carrier being in contact with the encapsulant has an adhesion promoting surface promoting adhesion between the chip carrier and the encapsulant.

9. The package according to claim 8 , wherein the adhesion promoting surface comprises at least one of the group consisting of a roughened surface, and an adhesion promoting coating, in particular an inorganic coating and/or an organic coating.

10. The package according to claim 1 , wherein one of the electrically conductive layers facing the at least one electronic chip is covered by a sinter layer, in particular a patterned sinter layer.

11. The package according to claim 1 , wherein one of the electrically conductive layers facing away from the at least one electronic chip is covered by a sinterable or sintered layer.

12. The package according to claim 1 , wherein one of the electrically conductive layers facing away from the at least one electronic chip is attached to a heatsink.

13. The package according to claim 1 , wherein the thermally conductive and electrically insulating core is configured for electrically insulating the at least one electronic chip with regard to an electronic environment of the package.

14. The package according to claim 1 , wherein the chip carrier forms part of an exterior surface of the package.

15. The package according to claim 1 , wherein at least two plate sections of the electrically conductive contact structure extend beyond the encapsulant and form power terminals for the electronic chip, and at least one lead section of the electrically conductive contact structure extends beyond the encapsulant and forms at least one signal terminal for the electronic chip.

16. The package according to claim 15 , wherein the at least two plate sections extend at different, in particular opposing, side faces beyond the encapsulant.

17. The package according to claim 16 , wherein the at least one lead section extends at the same side face beyond the encapsulant as one of the at least two plate sections.

18. The package according to claim 17 , wherein the at least one lead section and the one of the at least two plate sections extending at the same side face beyond the encapsulant are configured so that the at least one lead section is located in a recess of the other one of the at least two plate sections of an identical other package when the said plate sections of the packages are electrically connected.

19. The package according to claim 15 , wherein at least one of the at least two plate sections extends along at least 50%, in particular along at least 80% of a length of a side face of the encapsulant.

20. The package according to claim 15 , wherein at least one of the at least two plate sections comprises a locally raised bend portion, in particular having a wave profile.

21. The package according to claim 15 , wherein at least a portion of the at least one lead section extends substantially perpendicular to the at least two plate sections.

22. The package according to claim 15 , wherein at least one of the at least two plate sections is configured to be connected to a bus bar arrangement so that a magnetic flux associated with a current flowing into the package is coupled with magnetic flux of the current passing through the bus bar arrangement in opposite direction for an at least partial flux cancellation.

23. The package according to claim 1 , wherein the at least one electronic chip comprises at least one semiconductor power chip, in particular at least one insulated gate bipolar transistor chip.

24. The package according to claim 1 , wherein the electrically conductive contact structure comprises a leadframe.

25. The package according to claim 1 , wherein the electrically conductive contact structure comprises at least one downholder section configured for pressing the chip carrier downwardly towards a mold tool during molding.

26. The package according to claim 1 , comprising electrically conductive elements, in particular at least one of at least one bond wire, at least one bond ribbon, and at least one clip, electrically connecting the at least one electronic chip with the electrically conductive contact structure and/or the chip carrier with the electrically conductive contact structure.

27. The package according to claim 1 , wherein the encapsulant comprises a resin-based mold compound, in particular an epoxy resin-based mold compound.

28. An electronic device comprising at least two packages according to claim 1 , wherein in particular one of the power terminals of one of the packages is electrically coupled with one of the power terminals of the other one of the packages.

29. The device according to claim 28 , configured as at least one of the group consisting of a half-bridge, an H-bridge, an arrangement of three half-bridges, an arrangement of four half-bridges, and an inverter.

30. A package, comprising:
a chip carrier which comprises a thermally conductive and electrically insulating core covered on both opposing main surfaces thereof at least partially by a respective brazed electrically conductive layer, in particular an Active Metal Brazed (AMB) substrate;
at least one electronic chip mounted, in particular sintered, on the chip carrier;
an electrically conductive contact structure, in particular of a leadframe type, comprising at least one downholder section, in particular at least three downholder sections, configured as touchdown region for pressing the chip carrier towards a mold tool during molding for preventing

Assignees

• Infineon Technologies Ag

Inventors

• Pavier Mark
• Hable Wolfram
• Kessler Angela
• Sielaff Michael
• Pugatschow Anton
• Rimbert-Riviere Charles
• Sobkowiak Marco

Classifications

• H10W72/555

  of outermost layers of multilayered bond wires, e.g. material of a coating · CPC title

• H10W72/5524

  comprising aluminium [Al] · CPC title

• H10W72/534

  being rectangular · CPC title

• H10W72/522

  Multilayered bond wires, e.g. having a coating concentric around a core · CPC title

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title