Subsystem for configuration, security, and management of an adaptive system

Patent metadata

Field	Value
Publication number	US-2021124711-A1
Application number	US-201916666262-A
Country	US
Kind code	A1
Filing date	Oct 28, 2019
Priority date	Oct 28, 2019
Publication date	Apr 29, 2021
Grant date	—

Abstract

An integrated circuit (IC) can include a processor system configured to execute program code, a programmable logic, and a platform management controller coupled to the processor system and the programmable logic. The platform management controller is adapted to configure and control the processor system and the programmable logic independently.

First claim

What is claimed is:

1 . An integrated circuit, comprising:
a processor system configured to execute program code; a programmable logic; and a platform management controller coupled to the processor system and the programmable logic; wherein the platform management controller is adapted to configure and control the processor system and the programmable logic independently.

2 . The integrated circuit of claim 1 , wherein the platform management controller comprises:
a dedicated read-only memory; a first processor dedicated to executing first instructions stored in the dedicated read-only memory; a dedicated random access memory; and a second processor dedicated to executing second instructions stored in the dedicated random access memory.

3 . The integrated circuit of claim 2 , wherein each of the first processor and the second processor is implemented with redundancy.

4 . The integrated circuit of claim 2 , wherein the first processor executes the first instructions from the dedicated read-only memory to perform a first stage of a boot process that obtains and authenticates the second instructions from an external source and stores the second instructions in the dedicated random access memory for execution by the second processor.

5 . The integrated circuit of claim 4 , wherein the first processor establishes the platform management controller as a Root-of-Trust for the integrated circuit.

6 . The integrated circuit of claim 1 , wherein the platform management controller is powered independently of the processor system and the programmable logic.

7 . The integrated circuit of claim 6 , wherein the processor system is powered independently of the programmable logic.

8 . The integrated circuit of claim 6 , wherein the platform management controller is configured to power down the processor system and the programmable logic independently of one another and to power on the processor system and the programmable logic independently of one another.

9 . The integrated circuit of claim 1 , wherein:
the platform management controller comprises an interface and circuitry configured to detect a wake signal received via the interface; and wherein the platform management controller, in response to the wake signal, powers up a power domain of the integrated circuit that was previously powered down.

10 . The integrated circuit of claim 1 , wherein the platform management controller comprises a debug interface that is accessible from external to the integrated circuit and that is accessible independently of the processor system and the programmable logic.

11 . The integrated circuit of claim 1 , wherein:
the platform management controller comprises an error management interface configured to receive error notifications from the processor system and the programmable logic; and the error management interface is configured to perform at least one of generating a signal that is output from the integrated circuit and that indicates a detected error or generating an interrupt to a processor within the platform management controller.

12 . The integrated circuit of claim 1 , wherein the platform management controller is configured to program protection circuits implemented throughout the integrated circuit that control functional and physical isolation between subsystems of the integrated circuit, wherein the subsystems include the processor system and the programmable logic.

13 . The integrated circuit of claim 1 , wherein the platform management controller is configured to detect a temperature out of range event or a voltage out of range event for the integrated circuit.

14 . The integrated circuit of claim 13 , wherein the platform management controller is configured to erase the integrated circuit in response to detecting the temperature out of range event or the voltage out of range event.

15 . The integrated circuit of claim 1 , further comprising:
a first die including the platform management controller and at least one of the processor system or the programmable logic; and a second die including a slave platform management controller and at least the other of the processor system or the programmable logic.

16 . The integrated circuit of claim 1 , further comprising:
a processor array; and a programmable network-on-chip connecting the processor array with the programmable logic and the platform management controller.

17 . The integrated circuit of claim 16 , wherein the platform management controller is adapted to configure the programmable network-on-chip and configure the processor array using the programmable network-on-chip once configured.

18 . The integrated circuit of claim 1 , wherein the platform management controller is configured to detect tamper events occurring in the integrated circuit and, in response, initiating a lock-down state.

19 . A method, comprising:
providing a processor system on an integrated circuit, wherein the processor system is configured to execute program code; providing a programmable logic on the integrated circuit; and providing a platform management controller on the integrated circuit, wherein the platform management controller is coupled to the processor system and the programmable logic and is adapted to configure and control the processor system and the programmable logic independently.

20 . The method of claim 19 , further comprising:
providing, as part of the platform management controller, a dedicated read-only memory, a first processor dedicated to executing first instructions stored in the dedicated read-only memory, a dedicated random access memory, and a second processor dedicated to executing second instructions stored in the dedicated random access memory; and executing, using the first processor, the first instructions from the dedicated read-only memory to perform a first stage of a boot process that obtains and authenticates the second instructions from an external source and stores the second instructions in the dedicated random access memory for execution by the second processor.

Assignees

• Xilinx Inc

Inventors

• Ansari Ahmad R
• Ahmad Sagheer

Classifications

• G06F21/71

  to assure secure computing or processing of information · CPC title

• G06F15/7882 Primary

  for self reconfiguration · CPC title

• G06F21/575

  Secure boot · CPC title

• G06F15/7807

  System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package · CPC title

• G06F21/60

  Protecting data · CPC title