Virtualization of a reconfigurable data processor

Patent metadata

Field	Value
Publication number	US-10698853-B1
Application number	US-201916239252-A
Country	US
Kind code	B1
Filing date	Jan 3, 2019
Priority date	Jan 3, 2019
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

A reconfigurable data processor comprises an array of configurable units and a bus system configurable to define virtual machines. The system can partition the array of configurable units into a plurality of sets of configurable units, and block communications via the bus system between configurable units within a particular set and configurable units outside the particular set. A memory access controller can be connected to the bus system, configurable to confine access to memory outside the array of configurable units originating from within the particular set to memory space allocated to the particular.

First claim

What is claimed is:

1. A reconfigurable data processor, comprising:
an array of configurable units on one die or multichip module;
a bus system connected to the array of configurable units, configurable to partition the array of configurable units into a plurality of sets of configurable units, and block communications via the bus system between configurable units within a particular set and configurable units outside the particular set; and
a memory access controller connected to the bus system and configurable to confine access to memory outside the array of configurable units originating from within the particular set to memory space allocated to the particular set in the memory outside the array of configurable units.

2. The processor of claim 1 , including a plurality of memory access controllers, including the first mentioned memory access controller, memory access controllers in the plurality of memory access controllers being addressable nodes on the bus system, and the memory access controllers are configurable to confine access to memory outside the array of configurable units originating from within corresponding sets of configurable units in the plurality of sets of configurable units to memory space in the memory outside the array of configurable units allocated to the corresponding sets.

3. The processor of claim 1 , wherein sets of configurable units in the plurality of sets of configurable units are configurable to execute application graphs using virtual addresses, and the memory access controller includes or has access to a configurable table to translate virtual addresses in requests originating from an application graph executing within the particular set, to addresses in the memory space allocated to the particular set.

4. The processor of claim 1 , wherein the bus system comprises a grid of switches connected to configurable units in the array of configurable units, switches in the grid including circuits to partition the bus system.

5. The processor of claim 1 , wherein the bus system comprises a grid of switches connected to configurable units in the array of configurable units, switches in the grid including circuits configurable using port parameters, that enable and disable ports on the switches according to the port parameters.

6. The processor of claim 1 , wherein the bus system includes a top level network and an array level network,
the top level network connected to an external data interface for communication with memory outside of the array,
the array level network connected to configurable units in the array of configurable units, and wherein the memory access controller is connected to the array level network and to the top level network, and includes logic to route data transfers between the top level network and the array level network.

7. The processor of claim 6 , wherein the array level network comprises a grid of switches, and the switches in the grid, the configurable units in the array of configurable units and the memory access controller are addressable nodes on the array level network.

8. The processor of claim 6 , including a plurality of memory access controllers, including said first mentioned memory access controller, memory access controllers in the plurality of memory access controllers being addressable nodes in the array level network.

9. The processor of claim 8 , wherein the array level network comprises a grid of switches, and the switches in the grid, the configurable units in the array of configurable units and the memory access controllers in the plurality of memory access controllers are addressable nodes on the array level network.

10. The processor of claim 1 , wherein the array of configurable units includes a plurality of tiles of configurable units, and the bus system comprises switches on boundaries between the tiles including circuits to partition the bus system on the tile boundaries.

11. The processor of claim 10 , including a plurality of memory access controllers, including said first mentioned memory access controller, at least one memory access controller in the plurality of memory access controllers being operatively coupled to each tile in the plurality of tiles.

12. The processor of claim 1 , including
a configuration controller connected to the bus system, including logic to execute a configuration load process, including distributing configuration files to configurable units in individual sets of the configurable units in the array, wherein an application graph in one of the sets of configurable units is executable during the configuration load process in another set of configurable units.

13. The processor of claim 1 , including
a configuration controller connected to the bus system, including logic to execute a configuration unload process, including unloading state information from configurable units in individual sets, wherein an application graph in one of the sets of configurable units is executable during the configuration unload process in another set of configurable units.

14. A reconfigurable data processor, comprising:
an array of configurable units including a plurality of tiles of configurable units on one die or a multichip module;
a bus system connected to the array of configurable units, comprising boundary switches on tile boundaries between the tiles including circuits to configurable partition the bus system on the tile boundaries, and block communications via the bus system between configurable units within a particular tile and configurable units outside the particular tile; and
a plurality of memory access controllers connected to the bus system, memory access controllers in the plurality of memory access controllers being configurable to confine access to memory outside the array of configurable units originating from within corresponding tiles to memory space allocated to the corresponding tile in the memory outside the array of configurable units, and wherein at least one memory access controller in the plurality of memory access controllers is operatively coupled to each tile in the plurality of tiles.

15. The processor of claim 14 , wherein the bus system includes a top level network and an array level network,
the top level network connected to an external data interface for communication with memory outside of the array,
the array level network connected to configurable units in the array of configurable units, and wherein the memory access controllers in the plurality of memory access controllers are connected to the array level network and to the top level network, and include logic to route data transfers between the top level network and the array level network.

16. The processor of claim 15 , wherein the array level network comprises a grid of switches including said boundary switches, and the switches in the grid, the configurable units in the array of configurable units and the memory access controllers are addressable nodes on the array level network.

17. The processor of claim 14 , including a configuration controller connected to the bus system, including
logic to execute a configuration load process, including distributing configuration files to configurable units in individual sets of the configurable units in the array, wherein an application graph in one of the sets of configurable units is executable during the configuration load process in another set of configurable units; and
logic to execute a configuration unload process, including unloading state information from configurable units in individual sets, wherein an application graph in one of the se

Assignees

• Sambanova Systems Inc

Inventors

• Grohoski Gregory Frederick
• Jairath Sumti
• Luttrell Mark
• Prabhakar Raghu
• Sivaramakrishnan Ram
• Shah Manish K

Classifications

• G06F2212/657

  Virtual address space management · CPC title

• G06F15/7867 Primary

  with reconfigurable architecture · CPC title

• G06F15/7839

  with memory · CPC title

• G06F13/4027 Primary

  using bus bridges (G06F13/4022 takes precedence) · CPC title

• G06F13/1668

  Details of memory controller · CPC title