Multiprocessor system with improved secondary interconnection network

Patent metadata

Field	Value
Publication number	US-10747689-B2
Application number	US-201916252827-A
Country	US
Kind code	B2
Filing date	Jan 21, 2019
Priority date	Dec 13, 2012
Publication date	Aug 18, 2020
Grant date	Aug 18, 2020

Abstract

Embodiments of a multiprocessor system are disclosed that may include a plurality of processors interspersed with a plurality of data memory routers, a plurality of bus interface units, a bus control circuit, and a processor interface circuit. The data memory routers may be coupled together to form a primary interconnection network. The bus interface units and the bus control circuit may be coupled together in a daisy-chain fashion to form a secondary interconnection network. Each of the bus interface units may be configured to read or write data or instructions to a respective one of the plurality of data memory routers and a respective processor. The bus control circuit coupled with the processor interface circuit may be configured to function as a bidirectional bridge between the primary and secondary networks. The bus control circuit may also couple to other interface circuits and arbitrate their access to the secondary network.

First claim

What is claimed is:

1. An apparatus, comprising:
a plurality of routers forming a primary interconnection network;
a plurality of interface units coupled together in a daisy chain fashion to form a secondary interconnection network;
a plurality of processors coupled to the plurality of routers in an interspersed fashion, and wherein each processor of the plurality of processors is coupled to a respective one of the plurality of interface units; and
a bus controller coupled to a particular interface unit and a particular router each associated with a particular processor, wherein the bus controller is configured to pass a first message, received via the primary interconnection network, to the secondary interconnection network.

2. The apparatus of claim 1 , wherein the bus controller is further configured to pass a second message, received via the secondary interconnection network, to the primary interconnection network.

3. The apparatus of claim 1 , wherein the particular processor of the plurality of processors is configured to issue the first message on the primary interconnection network.

4. The apparatus of claim 3 , wherein the particular processor of the plurality of processors is configured to receive status information associated with the first message.

5. The apparatus of claim 1 , wherein the bus controller is further configured to arbitrate a plurality of requests to the particular interface unit of the plurality of interface units, wherein the plurality of requests originate from a plurality of circuit blocks.

6. The apparatus of claim 1 , further comprising a plurality of memories coupled to the plurality of routers and the plurality of processors.

7. A method, comprising:
receiving, by a bus controller, a first message via a primary interconnection network formed by a plurality of routers included in a multi-processor system that includes a plurality of a plurality of processors coupled to the plurality of routers in an interspersed fashion; and
forwarding, by the bus controller, the first message to a secondary interconnection network formed by a plurality of interface units coupled together in a daisy chain fashion, wherein the bus controller is coupled to a particular interface unit of the plurality of interface units and a particular router of the plurality of routers, wherein the particular interface unit and the particular router are each associated with a particular processor of the plurality of processors.

8. The method of claim 7 , further comprising forwarding, by the bus controller, a second message, received via the secondary interconnection network, to the primary interconnection network.

9. The method of claim 7 , further comprising, issuing, by the particular processor of the plurality of processors, the first message on the primary interconnection network.

10. The method of claim 9 , further comprising, receiving, by the particular processor of the plurality of processors, status information associated with the first message.

11. The method of claim 7 , arbitrating, by the bus controller, a plurality of requests to the particular interface unit of the plurality of interface units, wherein the plurality of requests originate from a plurality of circuit blocks.

12. The method of claim 7 , further comprising, by the particular interface unit, one or more messages on the secondary interconnection network.

13. The method of claim 7 , further comprising, performing an action based on a result of comparing two of messages received via the secondary interconnection network.

14. An apparatus, comprising:
a first integrated circuit chip including a bus controller coupled to a first secondary interconnection network, a first plurality of routers forming a first primary interconnection network and a first plurality of processors coupled to the first plurality of routers in an interspersed fashion; and
a second integrated circuit chip including a second plurality of processors that includes a particular processor configured to send a message to the bus controller via an inter-chip interconnect.

15. The apparatus of claim 14 , wherein the second integrated circuit chip includes a second plurality of routers forming a second primary interconnection network, wherein the second plurality of routers is coupled to the second plurality of processors in an interspersed fashion.

16. The apparatus of claim 15 , wherein the inter-chip interconnect is formed by coupling the first primary interconnection network to the second primary interconnection network.

17. The apparatus of claim 14 , where in the first integrated circuit chip further includes a plurality of interface units that form the first secondary interconnection network.

18. The apparatus of claim 17 , wherein the bus controller is further configured to relay the message, via the first secondary interconnection network, to a particular interface unit of the plurality of interface units coupled to a given processor of the first plurality of processors.

19. The apparatus of claim 18 , wherein the bus controller is further configured to arbitrate a plurality of requests to the particular interface unit of the plurality of interface units, wherein the plurality of requests originate from a plurality of circuit blocks.

20. The apparatus of claim 19 , wherein the plurality of circuit blocks includes a processor interface circuit, and a boot controller circuit.

Assignees

• Coherent Logix Inc

Inventors

• Dobbs Carl S
• Trocino Michael R

Classifications

• G06F15/17381

  Two dimensional, e.g. mesh, torus · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F13/4027

  using bus bridges (G06F13/4022 takes precedence) · CPC title

• G06F13/362

  with centralised access control · CPC title