Electronic control device and method of controlling logic circuit

Patent metadata

Field	Value
Publication number	US-2020050580-A1
Application number	US-201816606830-A
Country	US
Kind code	A1
Filing date	Mar 22, 2018
Priority date	Apr 24, 2017
Publication date	Feb 13, 2020
Grant date	—

Abstract

An electronic control device includes: a partially reconfigurable logic circuit in which a calculation unit which is reconfigured and executes calculation and a storage unit which stores calculation target date to be calculated by the calculation unit is configured; and a processing control unit which transmits circuit data for reconfiguring the calculation unit and the calculation target date to the logic circuit. When the processing control unit obtains next calculation target date which is the calculation target date relating to a next calculation unit which is the calculation unit after completion of reconfiguration, transmission of the next calculation target date to the storage unit is started regardless of whether the reconfiguration of the next calculation unit is completed, and upon completion of the reconfiguration, the next calculation unit performs calculation using the next calculation target date.

First claim

1 . An electronic control device, comprising:
a partially reconfigurable logic circuit in which a calculation unit which is reconfigured and executes calculation and a storage unit which stores calculation target date to be calculated by the calculation unit are configured; and a processing control unit which transmits circuit data for reconfiguring the calculation unit and the calculation target date to the logic circuit, wherein when the processing control unit obtains next calculation target date which is the calculation target date relating to a next calculation unit which is the calculation unit after completion of reconfiguration, transmission of the next calculation target date to the storage unit is started regardless of whether the reconfiguration of the next calculation unit is completed, and upon completion of the reconfiguration, the next calculation unit performs calculation using the next calculation target date.

2 . The electronic control device according to claim 1 , wherein
when the next calculation target date is generated by a processing of other than the calculation unit, and when the processing is completed, the processing control unit determines that the next calculation target date is obtained.

3 . The electronic control device according to claim 1 , wherein
when the processing control unit is capable of transmitting both the circuit data and the calculation target date to the logic circuit, the circuit data is preferentially transmitted to the logic circuit.

4 . The electronic control device according to claim 1 , wherein
when the processing control unit is capable of transmitting both the circuit data and the calculation target date to the logic circuit, based on circuit data transfer time which is time required for transmission of the circuit data to the logic circuit, and calculation data transfer time which is time required for transmission of the calculation target date to the logic circuit, the processing control unit determines one of the circuit data and the calculation target date is first transmission data to be transmitted first, and the other is post-transmission data to be transmitted later.

5 . The electronic control device according to claim 4 , wherein
the processing control unit determines post-transmission standby time based on a difference between the circuit data transfer time and the calculation data transfer time, and the processing control unit transmits the post-transmission data after only waiting for the post-transmission standby time after transmitting the first transmission data.

6 . The electronic control device according to claim 5 , wherein
the processing control unit determines the post-transmission standby time such that transmission of the circuit data and transmission of the calculation target date are simultaneously completed.

7 . The electronic control device according to claim 3 , wherein
a case where the circuit data is capable of being transmitted to the logic circuit is a case where the calculation in the calculation unit is completed, and a case where the calculation target date is capable of being transmitted to the logic circuit is a case where all calculation target date is read from the storage unit and the next calculation target date is obtained.

8 . The electronic control device according to claim 1 , wherein
a result storage unit which stores a calculation result of the calculation unit is further configured in the logic circuit, and when the calculation result of the calculation unit is stored in the result storage unit, the processing control unit starts to transmit the circuit data for reconfiguration of the calculation unit.

9 . A method of controlling a partially reconfigurable logic circuit in which a calculation unit which is reconfigured using circuit data to be transmitted and executes calculation and a storage unit which stores calculation target date to be calculated by the calculation unit is configured, the method comprising:
when next calculation target date which is the calculation target date relating to a next calculation unit which is the calculation unit after completion of reconfiguration is obtained, starting transmission of the next calculation target date to the storage unit regardless of whether the reconfiguration of the next calculation unit is completed; and upon completion of the reconfiguration, performing calculation using the next calculation target date by the next calculation unit.

10 . The method of controlling the logic circuit according to claim 9 , wherein
when the next calculation target date is generated by a processing of other than the calculation unit, and when the processing is completed, determining that the next calculation target date is obtained.

11 . The method of controlling the logic circuit according to claim 9 , wherein
when both the circuit data and the calculation target date is capable of being transmitted to the logic circuit, preferentially transmitting the circuit data to the logic circuit.

12 . The method of controlling the logic circuit according to claim 9 , wherein
when both the circuit data and the calculation target date is capable of being transmitted to the logic circuit, based on circuit data transfer time which is time required for transmission of the circuit data to the logic circuit, and calculation data transfer time which is time required for transmission of the calculation target date to the logic circuit, determining one of the circuit data and the calculation target date is first transmission data to be transmitted first, and the other is post-transmission data to be transmitted later.

13 . The method of controlling the logic circuit according to claim 12 , further comprising:
determining post-transmission standby time based on a difference between the circuit data transfer time and the calculation data transfer time; and transmitting the post-transmission data after only waiting for the post-transmission standby time after transmitting the first transmission data.

14 . The method of controlling the logic circuit according to claim 11 , wherein
a case where the circuit data is capable of being transmitted to the logic circuit is a case where the calculation in the calculation unit is completed, and a case where the calculation target date is capable of being transmitted to the logic circuit is a case where all calculation target date is read from the storage unit and the next calculation target date is obtained.

15 . The method of controlling the logic circuit according to claim 9 , further comprising:
further configuring a result storage unit which stores a calculation result of the calculation unit in the logic circuit; and when the calculation result of the calculation unit is stored in the result storage unit, transmitting the circuit data for reconfiguration of the calculation unit.

Assignees

• Hitachi Automotive Systems Ltd

Inventors

• Ueta Taisuke
• Tsutsumi Satoshi
• Endo Hideki
• Sakamoto Hideyuki

Classifications

• G06F8/61

  Installation · CPC title

• G06F9/30076

  to perform miscellaneous control operations, e.g. NOP · CPC title

• G06F15/7882 Primary

  for self reconfiguration · CPC title

• G05D1/0088

  characterized by the autonomous decision making process, e.g. artificial intelligence, predefined behaviours (using knowledge based models G06N5/00) · CPC title

• H03K19/173

  using elementary logic circuits as components · CPC title