Apparatus and methods for in-application programming of flash-based programmable logic devices

Patent metadata

Field	Value
Publication number	US-10642601-B2
Application number	US-201715432659-A
Country	US
Kind code	B2
Filing date	Feb 14, 2017
Priority date	Feb 28, 2011
Publication date	May 5, 2020
Grant date	May 5, 2020

Abstract

An architecture disposed in an integrated circuit for in-application programming of flash-based programmable logic devices includes a processor coupled to a processor system bus. An I/O peripheral is coupled to the processor over the system bus and is also coupled to an off-chip data source. A programmable logic device fabric includes flash-based programmable devices. A program controller is coupled to the flash-based programmable devices. An in-application programming controller is coupled to the program controller and is coupled to the processor over the system bus.

First claim

What is claimed is:

1. An architecture disposed in an integrated circuit for in-application programming of flash-based programmable logic devices comprising:
a processor in the integrated circuit and coupled to a processor system bus;
an I/O peripheral in the integrated circuit and coupled to the processor over the system bus and coupled to an off-chip data source;
a programmable logic array fabric in the integrated circuit and including flash-based programmable devices;
a programming controller in the integrated circuit configured to program the flash-based programmable devices; and
an in-application programming controller in the integrated circuit and coupled to the processor, the in-application programming controller separate from the programming controller and configured to control the operation of the programming controller in response to commands from the processor;
wherein the processor is configured to perform other tasks while the in-application programming controller executes the commands.

2. The architecture of claim 1 wherein the in-application programming controller is coupled to the processor over the system bus.

3. The architecture of claim 1 wherein the in-application programming controller is coupled to the processor over a JTAG interface.

4. The architecture of claim 1 wherein the in-application programming controller is configured as a state machine.

5. The architecture of claim 1 wherein the in-application programming controller is configured as a FIFO coupled between the system bus and the programming controller.

6. The architecture of claim 1 wherein the in-application programming controller communicates an interrupt to the processor.

7. The architecture of claim 1 wherein the programming controller is coupled to non-volatile memory elements associated with the programmable logic array fabric in the integrated circuit.

8. The architecture of claim 1 wherein the programming controller is coupled to non-volatile memory elements associated with user memory in the integrated circuit.

9. The architecture of claim 1 wherein the in-application program controller is configured to program nonvolatile memory by rows.

10. The architecture of claim 1 wherein the in-application program controller is configured to program nonvolatile memory by segments.

Assignees

• Microsemi Soc Corp

Inventors

• Narayanan Venkatesh
• Irving Kenneth R
• Kiu Ming-Hoe

Classifications

• G06F13/102

  where the program performs an interfacing function, e.g. device driver (G06F13/105 takes precedence; contention policies within device drivers G06F9/4881; scheduling within device drivers G06F9/52) · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• G06F8/654 Primary

  using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories · CPC title

• G06F15/7882

  for self reconfiguration · CPC title

• G06F13/24

  using interrupt (G06F13/32 takes precedence) · CPC title