Non-destructive bond line thickness measurement of thermal interface material on silicon packages

Patent metadata

Field	Value
Publication number	US-2021123729-A1
Application number	US-201916662158-A
Country	US
Kind code	A1
Filing date	Oct 24, 2019
Priority date	Oct 24, 2019
Publication date	Apr 29, 2021
Grant date	—

Abstract

Aspects of the invention include a non-destructive bond line thickness measurement of thermal interface material on silicon packages. A non-limiting example computer-implemented method includes receiving a chip mounted on a laminate and depositing a high-density material on the chip. The computer-implemented method deposits a thermal interface material on the chip and lids the chip, and the laminate with a lid. The computer-implemented method X-rays the lid, the chip, and the laminate to produce an X-ray and measures, using a processor, from the X-ray a bond line thickness of the TIM as a distance from a bottom of the lid to a top surface of the high-density material.

First claim

What is claimed is:

1 . A computer-implemented method comprising:
receiving a chip mounted on a laminate; depositing a high-density material on the chip; depositing a thermal interface material (“TIM”) on the chip; lidding the chip and the laminate with a lid; X-raying the lid, the chip, and the laminate to produce an X-ray; and measuring, using a processor, from the X-ray a bond line thickness (“BLT”) of the TIM as a distance from a bottom of the lid to a top surface of the high-density material.

2 . The computer-implemented method of claim 1 , wherein the high-density material is a material with sufficiently high mass density as to be detectable by X-rays.

3 . The computer-implemented method of claim 1 , wherein the high-density material is applied at a thickness of about 5 micrometers.

4 . The computer-implemented method of claim 1 , wherein the high-density material is applied to a plurality of points on the chip.

5 . The computer-implemented method of claim 1 , wherein the high-density material is applied as a layer across the chip.

6 . The computer-implemented method of claim 1 , wherein depositing a high-density material comprises cleaning a surface of the chip.

7 . The computer-implemented method of claim 6 , wherein depositing a high-density material comprises sputtering a metal seed layer on the surface of the chip.

8 . The computer-implemented method of claim 7 , wherein depositing a high-density material comprises patterning a plurality of islands on the surface of the chip.

9 . A system comprising:
a memory having computer readable instructions; and one or more processors for executing the computer readable instructions, the computer readable instructions controlling the one or more processors to perform operations comprising:
receiving a chip mounted on a laminate;
depositing a high-density material on the chip;
depositing a thermal interface material (“TIM”) on the chip;
lidding the chip and the laminate with a lid;
X-raying the lid, the chip, and the laminate to produce an X-ray; and
measuring, using a processor, from the X-ray a bond line thickness (“BLT”) of the TIM as a distance from a bottom of the lid to a top surface of the high-density material.

10 . The system of claim 9 , wherein the high-density material is a material with sufficiently high mass density as to be detectable by X-rays.

11 . The system of claim 9 , wherein the high-density material is applied at a thickness of about 5 micrometers.

12 . The system of claim 9 , wherein the high-density material is applied to a plurality of points on the chip.

13 . The system method of claim 9 , wherein the high-density material is applied as a layer across the chip.

14 . The system method of claim 9 , wherein depositing a high-density material comprises cleaning a surface of the chip.

15 . The system of claim 14 , wherein depositing a high-density material further comprises sputtering a metal seed layer on the surface of the chip.

16 . The system of claim 15 , wherein depositing a high-density material further comprises patterning a plurality of islands on the surface of the chip.

17 . A method, comprising:
receiving a chip mounted on a laminate; cleaning a surface of the chip; depositing a high-density material on the chip; depositing a thermal interface material (“TIM”) on the chip; lidding the chip and the laminate with a lid; X-raying the lid, the chip, and the laminate to produce an X-ray; and measuring from the X-ray a bond line thickness (“BLT”) of the TIM as a distance from a bottom of the lid to a top surface of the high-density material.

18 . The method of claim 17 , wherein the high-density material is a material with sufficiently high mass density as to be detectable by X-rays.

19 . The method of claim 17 , wherein the high-density material is applied at a thickness of about 5 micrometers.

20 . The method of claim 17 , wherein in place of depositing a high-density material on the chip a thin sheet of metal with high mass density is placed on the chip.

Assignees

• IBM

Inventors

• Zhang Hongqing
• Bunt Jay A
• Lewison David J
• Molinelli Acocella Joyce
• Luo Yu

Classifications

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P70/20

  Cleaning during device manufacture · CPC title

• H10P14/22

  using physical deposition, e.g. vacuum deposition or sputtering · CPC title

• H10W95/00

  Packaging processes not covered by the other groups of this subclass · CPC title

• H10W40/22

  characterised by their shape, e.g. having conical or cylindrical projections · CPC title