Semiconductor memory structure

Patent metadata

Field	Value
Publication number	US-9859283-B1
Application number	US-201715479290-A
Country	US
Kind code	B1
Filing date	Apr 5, 2017
Priority date	Mar 7, 2017
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A semiconductor memory structure includes a substrate including a memory cell region, a peripheral circuit region and a cell edge region defined thereon, and the cell edge region is defined in between the memory cell region and the peripheral circuit region. The semiconductor memory structure includes a plurality of active regions formed in the memory cell region, the cell edge region and the peripheral circuit region, and at least a dummy bit line formed on the active regions in the cell edge region. The dummy bit line is extended along a first direction and overlaps at least two active regions in a second direction. And the first direction and the second direction are perpendicular to each other. The dummy bit line includes a first inner line portion and an outer line portion, and the first inner line portion and the outer line portion include different widths and different spacers.

First claim

What is claimed is:

1. A semiconductor memory structure comprising:
a substrate comprising a memory cell region, a peripheral circuit region and a cell edge region defined in between the memory cell region and the peripheral circuit region;
a plurality of active regions formed in the memory cell region, the cell edge region and the peripheral circuit region; and
at least a dummy bit line formed on the active regions in the cell edge region, the dummy bit line being extended along a first direction and overlapping at least two active regions along a second direction, the first direction and the second direction being perpendicular to each other, the dummy bit line further comprising a first inner line portion and an outer line portion extended along the first direction, and a width of the first inner line portion being different from a width of the outer line portion.

2. The semiconductor memory structure according to claim 1 , further comprising a plurality of bit lines formed on the active regions in the memory cell region, the bit lines being extended along the first direction and arranged along the second direction.

3. The semiconductor memory structure according to claim 2 , further comprising a plurality of first contact plugs electrically connecting the bit lines to the active regions, respectively.

4. The semiconductor memory structure according to claim 2 , wherein the bit lines are electrically isolated from the dummy bit line.

5. The semiconductor memory structure according to claim 2 , further comprising at least a gate structure formed in the peripheral circuit region.

6. The semiconductor memory structure according to claim 5 , wherein the gate structure, the bit lines and the dummy bit line comprise a same material.

7. The semiconductor memory structure according to claim 5 , wherein the gate structure, the bit lines and the dummy bit line comprise a same height.

8. The semiconductor memory structure according to claim 1 , further comprising a second inner line portion and a curve portion connecting the first inner line portion and the second inner line portion.

9. The semiconductor memory structure according to claim 8 , further comprising a plurality of isolation structures formed in the substrate, and the active regions being electrically isolated from each other by the isolation structures.

10. The semiconductor memory structure according to claim 9 , wherein the curve portion is entirely formed on the isolation structures.

11. The semiconductor memory structure according to claim 8 , further comprising a plurality of second contact plugs electrically connecting the first inner line portion to the active regions.

12. The semiconductor memory structure according to claim 8 , wherein the outer line portion is electrically isolated from the active regions.

13. The semiconductor memory structure according to claim 1 , further comprising at least an insulating material formed in between the first inner line portion and the outer line portion.

14. The semiconductor memory structure according to claim 1 , wherein a width of a spacer formed on sidewalls of the first inner line portion is different from a width of a spacer formed on a sidewall of the outer line portion.

15. The semiconductor memory structure according to claim 1 , wherein a material of a spacer formed on a sidewall of the first inner line portion is different from a material of a spacer formed on sidewalls of the outer line portion.

16. The semiconductor memory structure according to claim 1 , wherein spacers formed on sidewalls at two sides of the outer line portion comprise different width.

17. The semiconductor memory structure according to claim 1 , wherein spacers formed on sidewalls at two sides of the outer line portion comprise different materials.

18. The semiconductor memory structure according to claim 1 , wherein the outer line portion overlaps at least two active regions.

Assignees

• United Microelectronics Corp
• Fujian Jinhua Integrated Circuit Co Ltd

Inventors

• Feng li-wei
• Ho Chien-Ting
• Tung Yu-Cheng

Classifications

• H01L27/1085

  Electricity · mapped topic

• H01L27/10897

  Electricity · mapped topic

• H01L27/10808

  Electricity · mapped topic

• H01L27/10885 Primary

  Electricity · mapped topic

• H01L27/10894

  Electricity · mapped topic