Manufacturing method of semiconductor memory device

Patent metadata

Field	Value
Publication number	US-2019019805-A1
Application number	US-201815987919-A
Country	US
Kind code	A1
Filing date	May 24, 2018
Priority date	Jul 11, 2017
Publication date	Jan 17, 2019
Grant date	—

Abstract

A manufacturing method of a semiconductor memory device includes the following steps. A semiconductor substrate is provided. A memory cell region and a peripheral region are defined on the semiconductor substrate. A dielectric layer is formed on the semiconductor substrate. A first trench penetrating the dielectric layer is formed on the memory cell region, and a second trench penetrating the dielectric layer is formed on the peripheral region. A metal conductive layer is formed. The first trench and the second trench are filled with the metal conductive layer for forming a bit line metal structure in the first trench and a first metal gate structure in the second trench. In the present invention, the replacement metal gate process is used to form the bit line metal structure for reducing the electrical resistance of the bit lines.

First claim

What is claimed is:

1 . A manufacturing method of a semiconductor memory device, comprising:
providing a semiconductor substrate, wherein a memory cell region and a peripheral region are defined on the semiconductor substrate; forming a dielectric layer on the semiconductor substrate; forming a first trench on the memory cell region, wherein the first trench penetrates the dielectric layer; forming a second trench on the peripheral region, wherein the second trench penetrates the dielectric layer; and forming a metal conductive layer, wherein the first trench and the second trench are filled with the metal conductive layer for forming a bit line metal structure in the first trench and a first metal gate structure in the second trench.

2 . The manufacturing method of the semiconductor memory device according to claim 1 , wherein the steps of forming the first trench and the second trench comprise:
forming a dummy bit line on the memory cell region of the semiconductor substrate and forming a dummy gate on the peripheral region of the semiconductor substrate before the step of forming the dielectric layer; and removing the dummy bit line for forming the first trench and removing the dummy gate for forming the second trench after the step of forming the dielectric layer.

3 . The manufacturing method of the semiconductor memory device according to claim 1 , further comprising:
forming a first barrier layer on the semiconductor substrate before the step of forming the metal conductive layer, wherein the first barrier layer is partly formed in the first trench and partly formed in the second trench; and removing the first barrier layer in the first trench before the step of forming the metal conductive layer.

4 . The manufacturing method of the semiconductor memory device according to claim 3 , further comprising:
forming a first work function layer on the first barrier layer before the step of forming the metal conductive layer, wherein the first work function layer is partly formed in the first trench and partly formed in the second trench; and removing the first work function layer in the first trench before the step of forming the metal conductive layer.

5 . The manufacturing method of the semiconductor memory device according to claim 4 , further comprising:
forming a third trench on the peripheral region, wherein the third trench penetrates the dielectric layer, and the third trench is filled with the metal conductive layer for forming a second metal gate structure in the third trench.

6 . The manufacturing method of the semiconductor memory device according to claim 5 , wherein the first barrier layer and the first work function layer are further formed in the third trench, and the manufacturing method of the semiconductor memory device further comprises:
removing the first work function layer in the third trench before the step of forming the metal conductive layer.

7 . The manufacturing method of the semiconductor memory device according to claim 6 , further comprising:
forming a second work function layer on the semiconductor substrate before the step of forming the metal conductive layer and after the step of removing the first work function layer in the third trench, wherein the second work function layer is partly formed in the first trench, partly formed in the second trench, and partly formed in the third trench; and removing the second work function layer in the first trench before the step of forming the metal conductive layer.

8 . The manufacturing method of the semiconductor memory device according to claim 1 , further comprising:
forming a gate dielectric layer on the semiconductor substrate, wherein the gate dielectric layer is at least partially formed on the peripheral region, and at least apart of the gate dielectric layer is located between the first metal gate structure and the semiconductor substrate.

9 . The manufacturing method of the semiconductor memory device according to claim 8 , wherein the gate dielectric layer is formed before the step of forming the first trench and the step of forming the second trench.

10 . The manufacturing method of the semiconductor memory device according to claim 8 , wherein the gate dielectric layer is partly formed in the first trench and partly formed in the second trench, and the manufacturing method of the semiconductor memory device further comprises:
removing the gate dielectric layer in the first trench before the step of forming the metal conductive layer.

11 . The manufacturing method of the semiconductor memory device according to claim 1 , further comprising:
forming a contact hole on the memory cell region, wherein the contact hole exposes a part of the semiconductor substrate; and forming a contact structure in the contact hole, wherein the contact structure is located between the bit line metal structure and the semiconductor substrate.

12 . The manufacturing method of the semiconductor memory device according to claim 11 , wherein the contact structure is formed before the step of forming the first trench and the step of forming the second trench.

13 . The manufacturing method of the semiconductor memory device according to claim 12 , further comprising:
forming a protection layer on the contact structure before the step of forming the first trench and the step of forming the second trench; and removing the protection layer on the contact structure before the step of forming the metal conductive layer.

14 . The manufacturing method of the semiconductor memory device according to claim 12 , wherein the contact structure includes a non-metal conductive material.

15 . The manufacturing method of the semiconductor memory device according to claim 14 , wherein the contact structure is electrically connected with the bit line metal structure.

16 . The manufacturing method of the semiconductor memory device according to claim 11 , wherein the contact hole is formed after the step of forming the first trench and the step of forming the second trench.

17 . The manufacturing method of the semiconductor memory device according to claim 16 , wherein the contact hole is filled with the metal conductive layer for forming the contact structure.

18 . The manufacturing method of the semiconductor memory device according to claim 17 , wherein a material of the contact structure is identical to a material of the bit line metal structure, and the contact structure is directly connected with the bit line metal structure.

19 . The manufacturing method of the semiconductor memory device according to claim 16 , further comprising:
forming a second barrier layer on the semiconductor substrate before the step of forming the metal conductive layer, wherein the second barrier layer is partly formed in the first trench and partly formed in the contact hole.

20 . The manufacturing method of the semiconductor memory device according to claim 19 , wherein the second barrier layer is further formed in the second trench.

Assignees

• United Microelectronics Corp
• Fujian Jinhua Integrated Circuit Co Ltd

Inventors

• Feng li-wei
• Tung Yu-Cheng

Classifications

• H01L27/1052

  Electricity · mapped topic

• H01L27/11573 Primary

  Electricity · mapped topic

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D64/018

  Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates · CPC title

• H10D64/017 Primary

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title