Resistive non-volatile memory and a method for sensing a memory cell in a resistive non-volatile memory

Patent metadata

Field	Value
Publication number	US-2019088317-A1
Application number	US-201715707350-A
Country	US
Kind code	A1
Filing date	Sep 18, 2017
Priority date	Sep 18, 2017
Publication date	Mar 21, 2019
Grant date	—

Abstract

An integrated circuit includes an array of resistive non-volatile memory cells having a plurality of word lines, a plurality of bit lines, and a plurality of source lines. The integrated circuit includes a sense amplifier coupled to a first bit line of the plurality of bit lines and a corresponding first source line of the plurality of source lines. When a memory cell coupled to the first bit line is selected for a read operation, the sense amplifier is configured to, during a calibration phase of the read operation, store a first voltage representative of a leakage current on the first source line. The sense amplifier is also configured to, during a sense phase of the read operation, apply the stored first voltage to the first bit line and provide a first sense amplifier output indicative of a logic state of the selected memory cell.

First claim

1 .- 10 . (canceled)

11 . An integrated circuit, comprising:
an array of resistive non-volatile memory cells comprising a plurality of word lines, a plurality of bit lines, and a plurality of source lines, wherein:
each non-volatile memory cell is coupled to a corresponding word line, a corresponding bit line, and a corresponding source line, and
each source line corresponds to one bit line and is shared by all memory cells of a memory column coupled to the corresponding one bit line;
a sense amplifier coupled to a first bit line of the plurality of bit lines and a corresponding first source line of the plurality of source lines, wherein, when a memory cell coupled to the first bit line is selected for a read operation, the sense amplifier is configured to:
during a calibration phase of the read operation of the memory cell, store a first voltage representative of a leakage current on the first source line, and
during a sense phase of the read operation, apply the stored first voltage to the first bit line and provide a first sense amplifier output indicative of a logic state of the selected memory cell.

12 . The integrated circuit of claim 11 , wherein the sense amplifier is configured to, during the sense phase of the read operation, apply a read current to a first end of the first bit line in which a second end of the first bit line, opposite the first end, is coupled to the stored first voltage.

13 . The integrated circuit of claim 11 , wherein the sense amplifier comprises a first amplifier coupled to the first source line and configured to, during the calibration phase of the read operation, generate the first voltage and transfer the first voltage to a first capacitive element.

14 . The integrated circuit of claim 13 , wherein the sense amplifier comprises a second amplifier, wherein during the sense phase of the read operation, the first capacitive element is coupled between the first bit line and an input of the second sense amplifier, wherein the second amplifier is configured to, during the sense phase of the read operation, provide the first sense amplifier output.

15 . A method of performing a read operation of a selected bit cell, wherein the read operation has a calibration phase and a subsequent sense phase, the method comprising:
during the calibration phase, storing a first voltage representative of a leakage current on a selected source line coupled to the selected bit cell; and during a sense phase:
coupling the stored first voltage to a selected bit line coupled to the selected memory cell,
providing a read current to the selected bit line, and
while coupling the stored first voltage to the selected bit line and providing the read current to the selected bit line, providing a first sense amplifier output indicative of a logic state of the selected memory cell.

16 . The method of claim 15 , wherein the method, during the calibration phase, further comprises:
coupling a first terminal of a first capacitor to the selected source line; sampling a voltage on the selected bit line; and using a first amplifier having a non-inverting input coupled to the first terminal of the first capacitor and having an output coupled to an inverting input of the first amplifier to generate the first voltage at the output of the first amplifier; and transferring the first voltage to a second capacitor having a first terminal coupled to the output of the first amplifier.

17 . The method of claim 16 , wherein the method, during the calibration phase, further comprises:
decoupling the first terminal of the first capacitor from the selected source line prior to the using the first amplifier to generate the first voltage.

18 . The method of claim 16 , wherein the method, during the calibration phase, further comprises:
limiting the leakage current on the selected source line to a predetermined reference current.

19 . The method of claim 16 , wherein the method, during the sense phase, further comprises:
coupling the first terminal of the second capacitor to the selected bit line; and using a second amplifier having a non-inverting input coupled to a second terminal of the second capacitor and an output coupled to the non-inverting input to provide the first sense amplifier output.

20 . The method of claim 19 , wherein the method, during the calibration phase, further comprises:
decoupling the output of the second amplifier from the non-inverting input of the second amplifier.

21 . The integrated circuit of claim 11 , wherein the sense amplifier includes:
a first capacitor, a first switch configured to couple the first bit line to a first terminal of the first capacitor in a first position and configured to decouple the first bit line from the first terminal of the first capacitor in a second position, a first amplifier having a non-inverting input coupled to the first terminal of the first capacitor and an inverting input coupled to an output of the first amplifier, a second switch configured to decouple the output of the first amplifier from the first bit line in a first position and to couple the output of the first amplifier to the first bit line in a second position, a second capacitor; a third switch configured to couple the output of the first amplifier to a first terminal of the second capacitor in a first position and to couple the first bit line to the first terminal of the second capacitor in a second position; a second amplifier having an inverting input coupled to a second terminal of the second capacitor; and a fourth switch configured to couple an output of the second amplifier to the inverting input of the second amplifier in a first position and to decouple the output of the second amplifier from the inverting input of the second amplifier in a second position.

22 . The integrated circuit of claim 21 , wherein, during the calibration phase of the read operation of a non-volatile memory cell coupled to the first bit line, the first, second, third, and fourth switches are in their respective first position.

23 . The integrated circuit of claim 22 , wherein, during the calibration phase of the read operation, the first switch is changed to its second position, while the first, third, and fourth switches remain in their respective first positions.

24 . The integrated circuit of claim 23 , wherein, after completion of the calibration phase, the second capacitor stores the first voltage representative of the leakage current on the first source line.

25 . The integrated circuit of claim 24 , wherein, during the sense phase of the read operation, subsequent to completion of the calibration phase, the second, third, and fourth switches are changed to their respective second positions and the output of the second amplifier provides a first output of the sense amplifier.

26 . The integrated circuit of claim 25 , wherein during the sense phase, the stored first voltage representative of the leakage current on the first source line is applied to a first end of the first bit line closest to the sense amplifier while a read current is applied to a second end of the first bit line, opposite the first end.

27 . The integrated circuit of claim 11 , further comprising a column decoder coupled between the array and the sense amplifier and configured to select the first bit line from a first subset of bit lines of the plurality of bit lines.

28 . The integrated circuit of claim 27 , further comprising a plurality of sense amplifiers coupled to the column decoder, wherein the column decoder

Assignees

• Nxp Usa Inc

Inventors

• Roy Anirban
• Pelley Perry

Classifications

• G11C13/004 Primary

  Reading or sensing circuits or methods · CPC title

• G11C11/1655

  Bit-line or column circuits · CPC title

• G11C13/0026

  Bit-line or column circuits · CPC title

• G11C2213/82

  Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials · CPC title

• G11C2013/0057

  Read done in two steps, e.g. wherein the cell is read twice and one of the two read values serving as a reference value · CPC title