Capacitive sensing and reference voltage scheme for random access memory

Patent metadata

Field	Value
Publication number	US-9767875-B2
Application number	US-201514823825-A
Country	US
Kind code	B2
Filing date	Aug 11, 2015
Priority date	Aug 11, 2015
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

A method uses a memory that includes a plurality of non-volatile memory (NVM) cells; a plurality of word lines; a plurality of bit lines; and an amplifier having an inverting input, a non-inverting input, and an output; and a capacitance coupled to the inverting input includes. A reference is coupled to the non-inverting input. The output of the amplifier is coupled to the inverting input of the amplifier while the non-inverting input receives the reference. The output is decoupled from the inverting input to store a voltage on the inverting input of the amplifier. A non-volatile (NV) element of a first NVM cell of the plurality of NVM cells is coupled to the non-inverting input. An output signal representative of the state of the NVM cell is provided.

First claim

What is claimed is:

1. A method of operating a memory, wherein the memory comprises a plurality of non-volatile memory (NVM) cells; a plurality of word lines; a plurality of bit lines; and an amplifier having an inverting input, a non-inverting input, and an output; and a capacitance coupled to the inverting input, the method comprising:
generating a reference having a magnitude using reference circuitry that includes a first portion and a second portion;
coupling the reference to the non-inverting input;
during a calibration operation:
coupling the output of the amplifier to the inverting input of the amplifier while the reference is coupled to the non-inverting input; and
decoupling the output from the inverting input whereby a voltage is stored on the inverting input of the amplifier;

during a sense operation:
coupling the first portion to the non-inverting input to the amplifier to provide a load;
decoupling the second portion from the non-inverting input to the amplifier;
coupling a non-volatile (NV) element of a first NVM cell of the plurality of NVM cells to the non-inverting input; and
providing an output signal representative of a logic state of the NVM cell.

2. The method of claim 1 , wherein the decoupling the output is further characterized by the voltage on the inverting input of the amplifier being equal to the magnitude the reference plus an offset of the amplifier.

3. The method of claim 2 , wherein the coupling of the output of the amplifier is performed in response to a calibration signal.

4. The method of claim 1 , wherein the coupling the reference is further characterized by the reference providing a voltage representative of an average of a logic high and a logic low of the NVM cells.

5. The method of claim 1 , wherein the first portion of the reference circuitry comprises a first pair of series-connected NV elements programmed to opposite logic states in parallel with a second pair of series-connected NV elements programmed to opposite logic states.

6. The method of claim 5 , wherein the reference circuitry is further characterized by the first and second pair of series connected NV elements that are in parallel are coupled between a first power supply terminal and the inverting input.

7. The method of claim 6 , wherein the coupling the reference further comprises coupling the load between a second power supply terminal and the non-inverting input.

8. The method of claim 7 , wherein the reference circuitry is further characterized by the second portion comprising a third pair of series-connected NV elements programmed to opposite logic states in parallel with a fourth pair of series-connected NV elements programmed to opposite logic states.

9. The method of claim 8 , further comprising decoupling the first and second pair of series-connected NV elements from the non-inverting input prior to the coupling the NV element of the first NVM cell to the non-inverting input of the amplifier, wherein the load is coupled to the non-inverting input during the coupling the NV element of the first NVM cell to the non-inverting input of the amplifier.

10. The method of claim 1 , wherein the coupling the NV element of the first NVM cell to the non-inverting input of the amplifier comprises coupling the NV element of the first NVM cell to a first bit line of the plurality of bit lines and coupling the first bit line to the non-inverting input.

11. A memory, comprising:
a plurality of word lines;
a plurality of source lines;
a plurality of bit lines; and
an array of comprising a plurality of non-volatile memory (NVM) cells and a plurality of reference circuits, wherein:
a first NVM cell of the plurality of NVM cells comprises a first non-volatile (NV) element and a coupling device, wherein the coupling device is coupled to a first bit line of the plurality of bit lines, a first word line of the plurality of word lines, and to the first NV element and wherein the first NV element is coupled to a first source line of the plurality of source lines; and
a first reference circuit of the plurality of reference circuits comprises a first pair of series-connected NV elements programmed to opposite logic states in parallel with a second pair of series connected NV elements programmed to opposite logic states;

an amplifier having an inverting input; a non-inverting input; an output; and a capacitance coupled to the inverting input in which:
in a calibration mode, the amplifier receives a reference voltage on the non-inverting input from the first reference circuit while the output is coupled to the inverting input and decouples the output from the inverting input in response to termination of the calibration mode whereby a reference is established on the inverting input; and
in a sensing mode in which a logic state of the first NV element is to be read, the non-inverting input is coupled to the first NV element and the first reference circuit is decoupled from the non-inverting input; and

a load coupled between a second power supply terminal and the non-inverting input in both the calibration mode and the sensing mode.

12. The memory of claim 11 , wherein, in the sensing mode, the first source line is coupled to a first power supply terminal.

13. The memory of claim 12 , wherein, in the calibration mode, the first reference circuit is coupled between the first power supply terminal and the non-inverting input.

14. The method of claim 13 , wherein the second power supply terminal is for a positive voltage and the first power supply terminal is for ground.

15. The memory of claim 14 , wherein the load comprises a third pair of series-connected NV elements programmed to opposite logic states in parallel with a fourth pair of series-connected NV elements programmed to opposite logic states.

16. The memory of claim 11 , further comprising a transistor that couples the first bit line to the non-inverting input during the read mode.

17. A method of operating a non-volatile memory (NVM), wherein the NVM comprises a plurality of NVM cells each having a non-volatile (NV) element; a plurality of word lines; a plurality of bit lines; and an amplifier having an inverting input, a non-inverting input, and an output; and a capacitance coupled to the inverting input, wherein the amplifier is characterized as having an offset, the method comprising:
performing a calibration by:
applying a reference and a load to the non-inverting input;
coupling the output of the amplifier to the inverting input during the applying the reference to the non-inverting input; and
decoupling the output of the amplifier from the inverting input after establishing an offset-compensated reference on the inverting input; and

performing a read of a selected NVM cell by:
decoupling the reference from the non-inverting input while the load remains coupled to the non-inverting input;
selecting an NVM cell;
coupling the non-inverting input to the NV element of the selected NVM cell; and
providing an output signal on the output representative of a logic state of the NV element.

18. The method of claim 17 , wherein the applying the reference is further characterized by the reference being applied by a first circuit comprising a first pair of series-connected NV elements programmed to opposite logic states in parallel with a second pair of series-connected NV elements programmed to opposite logic states, wherein the first circuit is coupled between the non-inverting input and a first power supply terminal.

19. The method of claim 18 , wherein the applyi

Assignees

• Freescale Semiconductor Inc
• Nxp Usa Inc

Inventors

• Roy Anirban
• Jew Thomas

Classifications

• G11C29/026

  in sense amplifiers · CPC title

• G11C11/1673 Primary

  Reading or sensing circuits or methods · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C11/1659

  Cell access · CPC title