Nonvolatile static random access memory (NVSRAM) system having a static random access memory (SRAM) array and a resistive memory array

Patent metadata

Field	Value
Publication number	US-9640256-B1
Application number	US-201615165041-A
Country	US
Kind code	B1
Filing date	May 26, 2016
Priority date	May 26, 2016
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

An integrated circuit (IC) device includes a static random access memory (SRAM) array, and a resistive memory (resistive memory) array. A first set of programmable resistive elements in the resistive memory array are used to store data from memory cells in the SRAM array. Sense amplifier circuitry is couplable to the SRAM array and the resistive memory array. An arbiter is configured to assert an resistive memory enable signal to couple the sense amplifier circuitry to the resistive memory array and decouple the sense amplifier circuitry from the SRAM array during a resistive memory read operation, and to couple the sense amplifier to the SRAM array and decouple the sense amplifier circuitry from the resistive memory array during an SRAM read operation.

First claim

What is claimed is:

1. An integrated circuit (IC) device comprising:
a static random access memory (SRAM) array;
a resistive memory resistive memory array, wherein a first set of programmable resistive elements in the resistive memory array are used to store data from memory cells in the SRAM array;
sense amplifier circuitry couplable to the SRAM array and the resistive memory array;
an arbiter configured to assert an resistive memory enable signal to
couple the sense amplifier circuitry to the resistive memory array and decouple the sense amplifier circuitry from the SRAM array during a resistive memory read operation, and
couple the sense amplifier to the SRAM array and decouple the sense amplifier circuitry from the resistive memory array during an SRAM read operation.

2. The IC device of claim 1 further comprising:
resistive memory pre-sense amplifier circuitry couplable between the resistive memory array and the sense amplifier circuitry, wherein the resistive memory pre-sense amplifier circuitry is coupled to the sense amplifier circuitry during the resistive memory read operation and decoupled from the sense amplifier circuitry during the SRAM read operation.

3. The IC device of claim 1 wherein:
a second set of the programmable resistive elements in the resistive memory array are used to store data other than data from the SRAM array.

4. The IC device of claim 1 wherein:
two of the programmable resistive elements of the resistive memory array are programmed in opposite states to store a logical bit of data from the SRAM array.

5. The IC device of claim 4 wherein the pre-sense amplifier comprises:
a first capacitive circuit and a second capacitive circuit;
calibration switches operable to:
couple a first of the two programmable resistive elements to the first capacitive circuit and a second of the two programmable resistive elements to the second capacitive circuit during a calibration mode, and
couple the first of the two programmable resistive elements to the second capacitive circuit and the second of the two programmable resistive elements to the first capacitive circuit during a sense mode of the resistive memory read operation.

6. The IC device of claim 5 further comprising:
a first current source and a second current source;
additional calibrations switches operable to:
during the calibration mode:
couple the first current source to the first of the two programmable resistive elements and the first capacitive circuit;
couple the second current source to the second of the two programmable resistive elements and the second capacitive circuit, and

during the sense mode:
couple the first current source to the second of the two programmable resistive elements and the first capacitive circuit;
couple the second current source to the first of the two programmable resistive elements and the second capacitive circuit.

7. The IC device of claim 4 further comprising:
a word line;
a true bit line;
a complementary bit line;
a first of the two programmable resistive elements is coupled to the true bit line and the word line; and
a second of the two programmable resistive elements is coupled the complementary bit line and the word line.

8. The IC device of claim 5 wherein the pre-sense amplifier circuit further includes:
a first buffer coupled to an output of the first capacitive circuit;
a second buffer coupled to an output of the second capacitive circuit.

9. The IC device of claim 8 wherein:
the first and second buffers are respective first and second pull-down transistors,
a gate electrode of the first pull-down transistor is coupled to the output of the first capacitive circuit, and
a gate electrode of the second pull-down transistor is coupled to the output of the second capacitive circuit.

10. The IC device of claim 8 , further comprising:
a true data line and a complementary data line are coupled to a column decoder for the memory cells in the SRAM array, to the sense amplifier, and to respective ones of the first and second buffers.

11. The device of claim 10 wherein the first and second capacitive circuits include switched capacitors.

12. A method of operating a static random access memory (SRAM) array and a resistive memory array, comprising:
during a read operation of the resistive memory array:
selecting programmable resistive elements of the resistive memory array;
coupling the selected programmable resistive elements of the resistive memory array to a pre-sense amplifier circuit;
decoupling the SRAM array from a sense amplifier circuit, and
sensing data from differential pairs of the selected programmable resistive elements in data buffers of the pre-sense amplifier circuit, wherein the data buffers are coupled to respective true data lines and complementary data lines of the sense amplifier circuit;

during a read operation of the SRAM array,
decoupling the resistive memory array from the sense amplifier circuit, and
sensing data on true and complementary bit lines of the SRAM array with the sense amplifier circuit.

13. The method of claim 12 further comprising:
coupling a first of the selected programmable resistive elements to a first capacitive circuit and a second of the selected programmable resistive elements to a second capacitive circuit during a calibration phase of the read operation of the resistive memory array, and
coupling the first of the selected programmable resistive elements to the second capacitive circuit and the second of the selected programmable resistive elements to the first capacitive circuit after the calibration phase of the read operation of the resistive memory array.

14. The method of claim 13 further comprising:
during the calibration phase of the read operation of the resistive memory array:
coupling a first current source to the first of the selected programmable resistive elements and the first capacitive circuit;
coupling a second current source to the second of the selected programmable resistive elements and the second capacitive circuit, and

after the calibration phase of the read operation of the resistive memory array:
coupling the first current source to the second of the selected programmable resistive elements and the first capacitive circuit;
coupling the second current source to the first of the selected programmable resistive elements and the second capacitive circuit.

15. The method of claim 12 further comprising:
storing data from the SRAM array in a first portion of the resistive memory array; and
storing data other than data from the SRAM array in a second portion of the resistive memory array.

16. The method of claim 12 further comprising:
selecting a first of the programmable resistive elements using a true bit line and a word line; and
selecting a second of the differential pair of programmable resistive elements using a complementary bit line and the word line.

17. The method of claim 16 further comprising:
programming the selected first and second of the programmable resistive elements of the resistive memory array in opposite states to store a logical bit of data from the SRAM array.

18. The method of claim 12 wherein the pre-sense amplifier circuit further includes:
during the read operation of the resistive memory array,
decoupling the SRAM array from the sense amplifier circuit through a column decoder or an arbiter;

during the read operation of the SRAM array,
coupling the SRAM array to the sense amplifier circuit through the column decoder or the arbiter.

Assignees

• Freescale Semiconductor Inc
• Nxp Usa Inc

Inventors

• Roy Anirban
• Choy Jon S
• Sadd Michael A

Classifications

• G11C11/419

  Read-write [R-W] circuits · CPC title

• G11C2013/0045

  Read using current through the cell · CPC title

• G11C14/0081 Primary

  and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell · CPC title

• G11C11/413

  Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction · CPC title

• G11C13/004

  Reading or sensing circuits or methods · CPC title