Magnetic random access memory (MRAM) and method of operation

Patent metadata

Field	Value
Publication number	US-9779795-B1
Application number	US-201615356879-A
Country	US
Kind code	B1
Filing date	Nov 21, 2016
Priority date	Nov 21, 2016
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

A memory device includes a first line coupled to a first terminal of a first memory cell, a second bit line coupled to a first terminal of a second memory cell, a sense amplifier coupled to a second end of the first bit line and a second end of the second bit line, a capacitor including a first terminal coupled to a first input of the sense amplifier and a second terminal coupled to a switch. The switch couples the second terminal of the capacitor to the second bit line during a calibration phase of a read operation and to the first bit line during a sense phase of the read operation. A current/voltage source drives current on the first bit line while the second line is floating during the calibration phase, and drives current on the second bit line while the first bit line is floating during the sense phase.

First claim

What is claimed is:

1. A memory device comprising:
a first bit line including a first end and a second end;
a first memory cell coupled between the first end and the second end of the first bit line;
a current source coupled to the first end of the first bit line;
a sense amplifier coupled to the second end of the first bit line;
a second bit line including a first end and a second end;
a second memory cell coupled between the first end and the second end of the second bit line;
the current source coupled to the first end of the second bit line;
the sense amplifier coupled to the second end of the second bit line;
a first capacitive element including a first terminal and a second terminal, the first terminal coupled to a first input of the sense amplifier; and
a first switch coupled to the second terminal of the first capacitive element, wherein
the first switch is placed in a first position during a first phase of operation during which current is driven on the first end of the first bit line while voltage is measured on the second end of the first bit line, and
the first switch is placed in a second position during a second phase of operation during which current is driven on the first end of the second bit line while voltage is measured on the second end of the second bit line.

2. The memory device of claim 1 wherein:
the first input of the sense amplifier is an inverting input; and
a second input of the sense amplifier is a non-inverting input coupled to a supply voltage.

3. The memory device of claim 1 further comprising:
a first word line; and
a first source line;
wherein
the first memory cell is coupled to the first bit line, the first word line and the first source line, and
the second memory cell is coupled to the second bit line, the first word line and the first source line.

4. The memory device of claim 3 wherein:
the first memory cell includes
a resistive storage element including a first terminal coupled to the first bit line and a second terminal coupled to a first current electrode of an access transistor, and
the access transistor further includes a gate electrode coupled to the first word line and a second current electrode coupled to the first source line.

5. The memory device of claim 4 wherein:
the second memory cell includes
a resistive storage element including a first terminal coupled to the second bit line and a second terminal coupled to a first current electrode of an access transistor, and
the access transistor further includes a gate electrode coupled to the first word line and a second current electrode coupled to the first source line.

6. The memory device of claim 4 wherein:
during the first phase of operation the second bit line is pre-charged, and
during the second phase of operation the first bit line is pre-charged.

7. The memory device of claim 1 further comprising:
a third bit line including a first end, and a second end coupled to the sense amplifier;
a fourth bit line including a first end, and a second end coupled to the sense amplifier;
a second capacitive element including a first terminal and a second terminal, the first terminal coupled to a second input of the sense amplifier; and
a second switch coupled to the second terminal of the second capacitive element,
wherein
the second switch is placed in a first position during the first phase of operation during which current is driven on the first end of the second bit line while voltage is measured on the second end of the second bit line and the second end of the fourth bit line, and
the second switch is placed in a second position during the second phase of operation during which current is also driven on the first end of the third bit line while voltage is measured on the second end of the first bit line and the second end of the third bit line.

8. The memory device of claim 7 further comprising:
a third switch including a first terminal coupled to the first terminal of the second capacitive element and the second input to the sense amplifier, and a second terminal coupled to ground, wherein the third switch is closed during the first phase of operation.

9. The memory device of claim 1 further comprising:
a fourth switch including a first terminal coupled to an output of the sense amplifier and a second terminal coupled to the first terminal of the first capacitive element and the first input of the sense amplifier, wherein the third switch is closed during the first phase of operation.

10. A method of operating a memory device comprising:
during a read operation:
placing a first switch in a first position during a calibration phase of the read operation;
driving current on a first end of a first bit line while voltage is measured by a sense amplifier on a second end of the first bit line during the calibration phase, wherein the first bit line is coupled to a first terminal of a first cell in the memory device and a capacitor is coupled between the first input to the sense amplifier and the first bit line while the voltage is measured on the second end of the first bit line;
placing the first switch in a second position during a sense phase of the read operation;
driving current on a first end of a second bit line while voltage is measured by the sense amplifier on a second end of the second bit line during the sense phase, wherein the second bit line is coupled to a first terminal of a second cell in the memory device and the capacitor is coupled between the first input to the sense amplifier and the second bit line while the voltage is measured on the second end of the second bit line.

11. The method of claim 10 further comprising:
pre-charging the second bit line before the current is driven on the first bit line; and
pre-charging the first bit line before the current is driven on the second bit line.

12. The method of claim 10 further comprising:
placing a second switch in a first position during the calibration phase;
driving the current on the first end of the first bit line (BL 1 ) and a first end of the second bit line while voltage is measured by the sense amplifier on the second end of the second bit line and a second end of a third bit line during the calibration phase;
placing the second switch in a second position during the sense phase; and
driving the current on the first end of the first bit line and the first end of the second bit line while voltage is measured by the sense amplifier on the second end of the first bit line and the second end of a fourth bit line during the sense phase.

13. The method of claim 10 wherein the second bit line is coupled to a first terminal of a second memory cell and the capacitor is coupled between the first input to the sense amplifier and the second bit line while the voltage is measured on the second end of the second bit line.

14. The method of claim 12 wherein the third bit line is coupled to a first terminal of a third cell in the memory device and a second capacitor is coupled between the first input to the sense amplifier and the third bit line while the voltage is measured on the second end of the third bit line.

15. The method of claim 10 further comprising:
coupling an output of the sense amplifier to the first input of the sense amplifier during the calibration phase; and
decoupling the output of the sense amplifier from the first input of the sense amplifier during the sense phase.

16. The method of claim 12 further comprising:
coupling a second input of the sense amplifier to a bias during the calibration phase; and
decoupling the second

Assignees

• Nxp Usa Inc

Inventors

• Sadd Michael A
• Roy Anirban

Classifications

• G11C11/1655

  Bit-line or column circuits · CPC title

• G11C11/16

  using elements in which the storage effect is based on magnetic spin effect · CPC title

• G11C11/15

  using multiple magnetic layers (G11C11/155 takes precedence) · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• G11C11/1673 Primary

  Reading or sensing circuits or methods · CPC title