Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2017194480-A1
Application number	US-201715464484-A
Country	US
Kind code	A1
Filing date	Mar 21, 2017
Priority date	Nov 30, 2015
Publication date	Jul 6, 2017
Grant date	—

Abstract

A semiconductor device includes first channel layers disposed over a substrate, a first source/drain region disposed over the substrate, a gate dielectric layer disposed on each of the first channel layers, a gate electrode layer disposed on the gate dielectric. Each of the first channel layers includes a semiconductor wire made of a first semiconductor material. The semiconductor wire passes through the first source/drain region and enters into an anchor region. At the anchor region, the semiconductor wire has no gate electrode layer and no gate dielectric, and is sandwiched by a second semiconductor material.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor device, comprising:
forming a fin structure in which first semiconductor layers and second semiconductor layers alternately stacked in a first direction; forming an isolation insulating layer over the fin structure; forming anchor regions by patterning the isolation insulating layer, thereby partially exposing the fin structure, end portions of the fin structure being buried in the anchor regions; at least partially removing the second semiconductor layers in the partially exposed fin structure; forming epitaxial source/drain structures on the exposed fin structure in source/drain regions; and forming a gate dielectric layer and a gate electrode layer around the exposed first semiconductor layers in a channel region, wherein, after the gate electrode layer is formed, the first semiconductor layers and the second semiconductor layers are alternately stacked at the anchor regions, and no gate electrode layer and no gate dielectric are included in the anchor regions.

2 . The method of claim 1 , wherein the first semiconductor layers are made of Si.

3 . The method of claim 2 , wherein the second semiconductor layers are made of SiGe.

4 . The method of claim 1 , wherein the first semiconductor layers are made of SiGe.

5 . The method of claim 4 , wherein the second semiconductor layers are made of Si.

6 . The method of claim 2 , wherein the epitaxial source/drain structures include at least one of SiP, SiCP and SiC.

7 . The method of claim 2 , wherein the epitaxial source/drain structures include SiGe.

8 . The method of claim 1 , wherein the second semiconductor layers are fully removed in the partially exposed fin structure, thereby exposing the first semiconductor layers.

9 . The method of claim 8 , wherein the epitaxial source/drain structures wrap around each of the exposed first semiconductor layers in the source/drain regions.

10 . The method of claim 1 , wherein the second semiconductor layers are only partially removed in the partially exposed fin structure.

11 . A semiconductor device, comprising:
first channel layers and a second channel layer disposed over a substrate; a first source/drain region and a second source/drain regions disposed over the substrate; a first gate dielectric layer disposed on each of the first channel layers and a second gate dielectric layer disposed on the second channel layer; and a gate electrode layer disposed on the first gate dielectric layer and a second gate dielectric layer, wherein: each of the first channel layers includes a semiconductor wire made of a first semiconductor material, the semiconductor wire passes through the first source/drain region and enters into an anchor region, and at the anchor region, the semiconductor wire has no gate electrode layer and no gate dielectric layer, and is sandwiched by a second semiconductor material different from the first semiconductor material.

12 . The semiconductor device of claim 11 , wherein:
the first semiconductor material is made of SiGe, and the second semiconductor material is Si.

13 . The semiconductor device of claim 11 , wherein:
the second channel layer include a stacked structure of the first semiconductor material and the second semiconductor material.

14 . The semiconductor device of claim 13 , wherein:
the first semiconductor material is made of Si, and the second semiconductor material is made of SiGe.

15 . The semiconductor device of claim 11 , wherein at the anchor region, the second channel layer has no gate electrode layer and no gate dielectric layer.

16 . A semiconductor device, comprising:
a fin structure having a channel layer, source/drain regions and anchored regions; source/drain epitaxial regions disposed on the source/drain regions; a gate dielectric layer disposed on the channel layer; and a gate electrode layer disposed on the gate dielectric layer, wherein: the anchored regions are embedded in anchor regions, the channel layer includes first semiconductor layers and second semiconductor layers alternately stacked in a vertical direction, widths of the first semiconductor layers in the channel layer are smaller than widths of the second semiconductor layer in the channel layer, the widths of the first semiconductor layers in the channel layer are smaller than widths of the first semiconductor layers in the anchor region, and at the anchor region, the fin structure has no gate electrode layer and no gate dielectric layer.

17 . The semiconductor device of claim 16 , wherein:
the first semiconductor layers are made of SiGe, and the second semiconductor layers are made of Si.

18 . The semiconductor device of claim 17 , wherein:
the first semiconductor layers are made of Si, and the second semiconductor layers are made of SiGe.

19 . The semiconductor device of claim 16 , wherein the source/drain epitaxial regions include at least one of SiP, SiCP and SiC.

20 . The semiconductor device of claim 16 , wherein the source/drain epitaxial regions include SiGe.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen I-Sheng
• Yeh Chih Chieh
• Wu Cheng-Hsien

Classifications

• H10D84/8311

  the IGFETs characterised by having different channel structures · CPC title

• H01L29/66795

  Electricity · mapped topic

• H01L29/456

  Electricity · mapped topic

• H01L29/41791

  Electricity · mapped topic

• H01L29/785 Primary

  Electricity · mapped topic