Methods for singulating semiconductor wafer

Patent metadata

Field	Value
Publication number	US-2017117185-A1
Application number	US-201715402192-A
Country	US
Kind code	A1
Filing date	Jan 9, 2017
Priority date	Oct 13, 2014
Publication date	Apr 27, 2017
Grant date	—

Abstract

Methods for dicing a wafer is presented. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies on main device regions and are spaced apart from each other by dicing channels on the first major surface of the wafer. A film is provided over first or second major surface of the wafer. The film covers at least areas corresponding to the main device regions. The method also includes using the film as an etch mask and plasma etching the wafer through exposed semiconductor material of the wafer to form gaps to separate the plurality of dies on the wafer into a plurality of individual dies.

First claim

What is claimed is:

1 . A method for dicing a wafer comprising:
providing a wafer having first and second major surfaces, wherein the wafer is prepared with a plurality of dies on main device regions and are spaced apart from each other by dicing channels on the first major surface of the wafer, wherein
the first major surface is an active surface and the second major surface is a passive surface,
the wafer is processed to include a passivation layer formed over the active surface of the wafer, and
the passivation layer extends over the main device regions and the dicing channels;
providing a protective film over the second major surface of the wafer, wherein the protective film is patterned to cover areas of the wafer corresponding to the main device regions and expose areas of the wafer corresponding to the dicing channels; using the patterned protective film as an etch mask, performing a plasma etching process to remove exposed semiconductor material of the wafer and form trenches within the wafer, wherein the trenches extend through the wafer to expose portions of the passivation layer extending over the dicing channels; and performing a non-etching process on the passivation layer to singulate the plurality of dies.

2 . The method of claim 1 wherein the first major surface of the wafer is where integrated circuits are defined and the second major surface of the wafer is a back surface of the wafer.

3 . The method of claim 1 wherein providing the protective film comprises forming a thermoplastic polymer based resin film on the second major surface of the wafer.

4 . The method of claim 1 wherein patterning the protective film comprises selectively removing portions of the protective film disposed over areas corresponding to the dicing channels of the wafer, wherein the trenches formed by the plasma etching includes about a same width as the dicing channels.

5 . The method of claim 1 comprising providing a support platform and attaching the first major surface of the wafer to the support platform.

6 . The method of claim 5 wherein the wafer comprises one or more monitoring patterns formed in the dicing channels of the wafer and the one or more monitoring patterns contact the support platform when the first major surface of the wafer is attached to the support platform.

7 . The method of claim 6 wherein singulating the plurality of dies comprises removing each die from the support platform, wherein the monitoring patterns remain on the support platform after the individual dies are removed.

8 . The method of claim 1 wherein the wafer comprises one or more monitoring patterns formed in the dicing channels of the wafer.

9 . The method of claim 8 wherein the passivation layer covers the main device regions and the one or more monitoring patterns on the active surface of the wafer.

10 . The method of claim 1 wherein the plasma etching process is highly selective to silicon material and does not etch through the passivation layer.

11 . The method of claim 1 wherein the non-etching process is performed through the trenches formed during the plasma etching process to severe and separate the passivation layer of individual dies.

12 . The method of claim 11 wherein the non-etching process comprises a die pick up process, wherein the passivation layer of each die is separated by a pulling force during the die pick up process.

13 . The method of claim 11 wherein performing the non-etching process comprises applying a jet of air blow or laser beam to the portions of passivation layer exposed by the trenches.

14 . A method for dicing a wafer comprising:
providing a wafer having first and second major surfaces, wherein the wafer is prepared with a plurality of dies on main device regions and are spaced apart from each other by dicing channels on the first major surface of the wafer, wherein
the first major surface is an active surface and the second major surface is a passive surface,
the wafer is processed to include a passivation layer formed over the active surface of the wafer, and
the passivation layer extends over the main device regions and the dicing channels;
providing a backside protective layer on the second major surface of the wafer, wherein the backside protective layer is patterned to remove portions of the backside protective layer disposed over areas corresponding to the dicing channels, wherein the patterned backside protective layer partially exposes the second major surface of the wafer; performing a plasma etching process to remove semiconductor material of the wafer exposed by the patterned backside protective layer, the plasma etching process forms gaps extending through the wafer to expose portions of the passivation layer, wherein the passivation layer is not removed; and performing a non-etching process on the passivation layer to singulate the plurality of dies.

15 . The method of claim 14 wherein the plasma etching process is highly selective to silicon material, wherein the passivation layer includes non-silicon material.

16 . The method of claim 14 comprising providing a support platform and attaching the first major surface of the wafer to the support platform, wherein the support platform does not extend to cover end portions of the first major surface of the wafer.

17 . The method of claim 16 comprising providing a temporary support carrier and attaching the support platform to a top surface of the temporary support carrier.

18 . The method of claim 17 wherein performing the non-etching process includes performing a die pick up process to remove individual dies from the support platform, wherein the die pick process severe portions of the passivation layer by a pulling force.

19 . The method of claim 14 wherein performing the non-etching process comprises applying a jet of air blow or laser beam to the passivation layer through the gaps formed during the plasma etching process to severe portions of the passivation layer.

20 . The method of claim 14 wherein the wafer comprises one or more monitoring patterns formed in the dicing channels of the wafer, wherein the plasma etching process does not remove the one or more monitoring patterns in the dicing channels.

Assignees

• Utac Headquarters Pte Ltd

Inventors

• Nelson William John
• Suthiwongsunthorn Nathapong
• Ho Beng Yeung
• Ong Poh Leng Wilson

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W46/503

  Located in scribe lines · CPC title

• H10W46/301

  for alignment · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title