Method, apparatus, and system for passive die strain measurement

Patent metadata

Field	Value
Publication number	US-2017052014-A1
Application number	US-201514830214-A
Country	US
Kind code	A1
Filing date	Aug 19, 2015
Priority date	Aug 19, 2015
Publication date	Feb 23, 2017
Grant date	—

Abstract

At least one method, apparatus, and system for determining a distance between layers of a semiconductor device and, if desired, modifying a semiconductor device manufacturing process in view of the determined distance. The system comprises and the methods make use of a test circuit comprising a resistor, at least one of an inductor and a capacitor, a first terminal and a second terminal each configured to electrically connect to a first layer circuit and a second layer circuit of a semiconductor device.

First claim

What is claimed is:

1 . A method, comprising:
providing an input voltage (V in ) to a resistor of a test circuit, wherein the test circuit comprises the resistor in series with an impedance unit, and the test circuit comprises a first terminal in contact with a first layer circuit of a semiconductor device and a second terminal in contact with a second layer circuit of the semiconductor device; receiving an output voltage (V out ) from the test circuit; and determining at least one of a distance between the first layer and the second layer or a stress in at least one of the first layer and the second layer, based on V out and V in .

2 . The method of claim 1 , wherein the resistor has a resistance from about 50Ω to about 250Ω.

3 . The method of claim 1 , wherein the impedance portion comprises an inductor and a capacitor.

4 . The method of claim 3 , wherein the inductor has a metal width equal to or less than about 500 nm.

5 . The method of claim 1 , further comprising providing an indicator of the distance to a process controller configured to manufacture a second iteration of the semiconductor device.

6 . A semiconductor device, comprising:
a first layer comprising a first layer circuit; a second layer comprising a second layer circuit; and a test circuit, comprising:
a resistor and an impedance unit, wherein the resistor is in series with the impedance unit;
a first terminal electrically connected to the first layer circuit;
a second terminal electrically connected to the second layer circuit;
a voltage input node electrically connected to the resistor; and
a voltage output node.

7 . The semiconductor device of claim 6 , wherein the resistor has a resistance from about 50Ω to about 250Ω.

8 . The semiconductor device of claim 6 , wherein the impedance portion comprises an inductor and a capacitor.

9 . The semiconductor device of claim 8 , wherein the inductor has a metal width equal to or less than about 500 nm.

10 . The semiconductor device of claim 6 , wherein the test circuit has a width equal to or less than about 50 μm.

11 . The semiconductor device of claim 6 , wherein first layer and the second layer are adjacent.

12 . The semiconductor device of claim 6 , further comprising one or more features extending vertically from an uppermost layer of the semiconductor device, wherein the test circuit is located under at least one of the one or more features.

13 . The semiconductor device of claim 6 , further comprising two or more features extending vertically from an uppermost layer of the semiconductor device, wherein the test circuit is located between two of the two or more features.

14 . The semiconductor device of claim 6 , wherein the semiconductor device is a die having an inscribe radius defining an inscribe circle, wherein the test circuit is located equal to or less than about 0.7 times the inscribe radius from the center of the inscribe circle.

15 . A system, comprising:
a test circuit, comprising:
a resistor and an impedance portion, wherein the resistor is in series with the impedance portion;
a first terminal electrically connected to a first layer circuit in a first layer of a semiconductor device;
a second terminal electrically connected to a second layer circuit in a second layer of the semiconductor device;
a voltage input node electrically connected to the resistor; and
a voltage output node;
an interface configured to receive a directive to sense a stress and deliver an input voltage (V in ) to the voltage input node of the test circuit in response to the directive; and a stress data unit, configured to receive an output voltage (V out ) from the voltage output of the test circuit and determine at least one of a distance between the first layer and the second layer or a stress of at least one of the first layer and the second layer, based on V out and V in .

16 . The system of claim 15 , wherein the resistor has a resistance from about 50Ω to about 250Ω.

17 . The system of claim 15 , wherein the impedance portion comprises an inductor and a capacitor.

18 . The system of claim 17 , wherein the inductor has a metal width equal to or less than about 500 nm.

19 . The system of claim 15 , wherein the test circuit has a width equal to or less than about 50 μm.

20 . The system of claim 15 , further comprising:
a process controller, configured to provide an instruction set comprising a plurality of parameters for manufacture of the semiconductor device to a manufacturing system; the manufacturing system, configured to manufacture the semiconductor device according to the instruction set; a process modeling unit, configured to receive the distance between the first layer and the second layer from the stress data unit and compare the distance to a specified distance; a process modification unit, configured to modify at least one parameter of the instruction set if the distance is substantially different from the specified distance, yielding a modified instruction set, and provide the modified instruction set to the process controller; wherein the process controller is further configured to provide the modified instruction set to the manufacturing unit for manufacture of a subsequent iteration of the semiconductor device.

Assignees

• Globalfounries Inc
• Globalfoundries Inc

Inventors

• Smith Ryan Scott

Classifications

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P72/0616

  Monitoring of warpages, curvatures, damages, defects or the like · CPC title

• G01B7/14 Primary

  for measuring distance or clearance between spaced objects or spaced apertures (G01B7/30 takes precedence) · CPC title