Printed circuit board and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2016374197-A1
Application number	US-201615139698-A
Country	US
Kind code	A1
Filing date	Apr 27, 2016
Priority date	Jun 18, 2015
Publication date	Dec 22, 2016
Grant date	—

Abstract

A printed circuit board includes: an insulating layer including a cavity formed therein, the cavity being recessed into the insulating layer from a top surface of the insulating layer; a first circuit layer formed inside the insulating layer such that a portion of the first circuit layer is disposed within the cavity; a second circuit layer disposed above the insulating layer; a first surface-treated layer disposed above the portion of the first circuit layer disposed within the cavity; and a second surface-treated layer disposed above the second circuit layer.

First claim

What is claimed is:

1 . A printed circuit board comprising:
an insulating layer comprising a cavity formed therein, the cavity being recessed into the insulating layer from a top surface of the insulating layer; a first circuit layer formed inside the insulating layer such that a portion of the first circuit layer is disposed within the cavity; a second circuit layer disposed above the insulating layer; a first surface-treated layer disposed above the portion of the first circuit layer disposed within the cavity; and a second surface-treated layer disposed above the second circuit layer.

2 . The printed circuit board of claim 1 , wherein the first surface-treated layer is constructed of a material that does not react with an etchant that reacts with the second circuit layer.

3 . The printed circuit board of claim 1 , further comprising a first protective layer disposed above the insulating layer within the cavity and surrounding and protecting the first circuit layer, wherein the first protective layer is formed to expose an upper surface of the first surface-treated layer to an outside environment.

4 . The printed circuit board of claim 1 , further comprising a first protective layer disposed above the insulating layer within the cavity and between a lateral surface of the second insulating layer and a lateral surface of the first circuit layer.

5 . The printed circuit board of claim 1 , further comprising a second protective layer disposed above the insulating layer and surrounding and protecting the second circuit layer, wherein the second protective layer is formed to expose an upper surface of the second surface-treated layer to an outside environment.

6 . The printed circuit board of claim 1 , wherein the portion of the first circuit layer disposed in the cavity forms connection pads configured to be electrically connected with an electronic component to be mounted thereon.

7 . A method of manufacturing a printed circuit board, comprising:
forming a first circuit layer above a first insulating layer such that a portion of the first circuit layer is disposed in a cavity area of the first insulating area and is exposed to an outside environment; forming a first surface-treated layer above the portion of the first circuit layer disposed in the cavity area; forming a second insulating layer above the first insulating layer, the second insulating layer comprising a cavity formed at a portion thereof corresponding to the cavity area; forming a second circuit layer above the second insulating layer; and forming a second surface-treated layer above the second circuit layer.

8 . The method of claim 7 , further comprising, prior to the forming of the first surface-treated layer, forming a first protective layer above the first insulating layer in the cavity area,
wherein the first protective layer is formed to surround the portion of the first circuit layer disposed in the cavity area and to expose a portion of an upper surface of the first circuit layer to the outside environment.

9 . The method of claim 7 , further comprising, after the forming of the first surface-treated layer, forming a first protective layer above the first insulating layer in the cavity area,
wherein the first protective layer is formed between a lateral surface of the second insulating layer and a lateral surface of the first circuit layer.

10 . The method of claim 7 , wherein the forming of the first surface-treated layer comprises constructing the first surface-treated layer of a material that does not react with an etchant reacting with the second circuit layer.

11 . The method of claim 7 , wherein the forming of the second circuit layer comprises forming the second circuit layer using a tenting method.

12 . The method of claim 7 , wherein, the forming of the second insulating layer comprises laminating the second insulating layer having the cavity formed therein and a metal foil covering an upper part of the second insulating layer including the cavity above the first insulating layer.

13 . The method of claim 12 , wherein the forming of the second circuit layer comprises:
forming a plated layer above the metal foil by performing electroplating; forming an etching resist patterned to expose the second circuit layer and a portion corresponding to the cavity; removing portions of the metal foil exposed by the etching resist and the plated layer by use of an etchant; and removing the etching resist.

14 . The method of claim 7 , further comprising, prior to the forming of the second surface-treated layer, forming a second protective layer above the second insulating layer,
wherein the second protective layer is formed to surround the second circuit layer and to expose an upper surface of a portion of the second circuit layer to the outside environment.

15 . The method of claim 14 , wherein, in the forming of the second surface-treated layer, the second surface-treated layer is formed on the upper surface of the portion of the second circuit layer exposed to the outside environment by the second protective layer.

16 . The method of claim 7 , further comprising:
forming a plated resist above the first circuit layer within the cavity, prior to the forming of the second surface-treated layer; and removing the plated resist, after the forming of the second surface-treated layer.

17 . The method of claim 7 , wherein the portion of the first circuit layer disposed in the cavity area forms connection pads configured to be electrically connected with an electronic component to be mounted thereon.

Assignees

• Samsung Electro Mech

Inventors

• Lee Jae-Ean
• Mok Jee-Soo
• Ko Young-Gwan
• Jung Soon-Oh
• Ko Kyung-Hwan
• Baek Yong-Ho

Classifications

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/68

  Shapes or dispositions thereof · CPC title

• H05K3/061

  Etching masks · CPC title

• H05K3/188

  by direct electroplating · CPC title