Bumpless die-package interface for bumpless build-up layer (bbul)

Patent metadata

Field	Value
Publication number	US-2016233166-A1
Application number	US-201314367711-A
Country	US
Kind code	A1
Filing date	Aug 21, 2013
Priority date	Aug 21, 2013
Publication date	Aug 11, 2016
Grant date	—

Abstract

Embodiments of the present disclosure are directed towards bumpless interfaces to an embedded silicon die, in integrated circuit (IC) package assemblies. In one embodiment, a method includes forming a surrounding portion of dielectric material defining a cavity therein; placing at least one die in the cavity, the die including a contact; depositing a dielectric material on the die and the surrounding portion; etching the dielectric material to expose the contact; and depositing conductive material onto the contact. Other embodiments may he described and/or claimed.

First claim

1 . A method of fabricating a package assembly, the method comprising:
forming a surrounding portion of dielectric material defining a cavity therein; placing at least one die in the cavity, the die including a contact; depositing a dielectric material on the die and the surrounding portion; etching the dielectric material to expose the contact; and depositing conductive material onto the contact.

2 . The method of claim 1 , wherein:
forming the surrounding portion includes forming a conductive path through the surrounding portion.

3 . The method of claim 2 , wherein:
forming the conductive path includes forming a redistribution layer.

4 . The method of claim 1 , wherein:
forming the surrounding portion is performed by lamination.

5 . The method of claim 1 , wherein:
depositing the dielectric material is performed by lamination.

6 . The method of claim 1 , wherein:
depositing the dielectric material substantially fills portions of the cavity disposed between the die and the surrounding portion of dielectric material.

7 . The method of claim 1 , wherein:
depositing the dielectric material on the die and the surrounding portion forms a uniform surface.

8 . The method of claim 1 , wherein:
placing the at least one die includes placing a die having a passivation layer disposed on the contact and an opening disposed in the passivation layer to expose the contact; depositing the dielectric material fills the opening; and etching the dielectric material removes the dielectric material from the opening.

9 . The method of claim 1 , wherein:
placing the at least one die in the cavity includes placing a plurality of dies in the cavity.

10 . The method of claim 9 , wherein:
each of the plurality of dies includes a recessed exposed contact.

11 . The method of claim 1 , wherein:
the contact is a recessed exposed contact.

12 . The method of claim 4 , wherein:
forming the surrounding portion includes forming a conductive path through the surrounding portion.

13 . The method of claim 2 , wherein:
forming the surrounding portion is performed by lamination.

14 . The method of claim 2 , wherein:
depositing the dielectric material on the die and the surrounding portion forms a uniform surface.

15 . The method of claim 1 , wherein:
etching the dielectric material to expose the contact, exposes at least one additional contact electrically coupled with a conductive path through the surrounding portion.

16 . A package assembly comprising:
a die located in a cavity defined by a surrounding portion of dielectric material, the die having a die contact; a conductive path through the surrounding portion; a dielectric layer disposed on the die and the surrounding portion; and at least one interconnect formed through the dielectric layer and electrically coupled with the die contact, the interconnect being configured to route electrical signals of the die.

17 . The package assembly of claim 16 , wherein the dielectric layer encapsulates the die.

18 . The package assembly of claim 16 , wherein:
the conductive path through the surrounding portion is configured to electrically couple a first package-level interconnect on a first side of the package assembly to a second package-level interconnect on a second side of the package assembly.

19 . The package assembly of claim 16 , further comprising a second die located in the cavity.

20 . The package assembly of claim 16 , wherein the package assembly is a first package assembly having a first side and a second side disposed opposite to the first side, the first package assembly further comprising:
one or more build-up layers disposed on the dielectric layer, wherein the one or more build-up layers are disposed between the die and the first side; and one or more package-level interconnects disposed on the first side and configured to route the electrical signals of the die between the first package assembly and a circuit board.

21 . The package assembly of claim 20 , further comprising:
package-on-package (PoP) pads disposed on the second side and electrically coupled with the conductive path, the PoP pads being configured to route electrical signals between the circuit board and a second package assembly through the first package assembly.

22 . A computing device comprising:
a circuit board; and a package assembly having a first side and a second side disposed opposite to the first side, the first side being coupled with the circuit board using one or more package-level interconnects disposed on the first side, the package assembly including a die located in a cavity defined by a surrounding portion of dielectric material, the die having a die contact; a conductive path through the surrounding portion; a dielectric layer disposed on the die and the surrounding portion; and at least one interconnect formed through the dielectric layer and electrically coupled with the die contact, the interconnect being configured to route electrical signals of the die.

23 . The computing device of claim 22 , further comprising a second die located in the cavity.

24 . The computing device of claim 22 wherein:
the conductive path through the surrounding portion is configured to electrically couple a first package-level interconnect on a first side of the package assembly to a second package-level interconnect on a second side of the package assembly.

25 . The computing device of claim 22 , wherein:
the computing device is a mobile computing device including one or more of an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, or a camera coupled with the circuit board.

Assignees

• Teh Weng Hong
• Guzek John S
• Sankman Robert L
• Intel Corp

Inventors

• Teh Weng Hong
• Guzek John S
• Sankman Robert L

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title