Semiconductor device and method of balancing surfaces of an embedded PCB unit with a dummy copper pattern

Patent metadata

Field	Value
Publication number	US-9449943-B2
Application number	US-201414329464-A
Country	US
Kind code	B2
Filing date	Jul 11, 2014
Priority date	Oct 29, 2013
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

A semiconductor device has a substrate. A conductive via is formed through the substrate. A plurality of first contact pads is formed over a first surface of the substrate. A plurality of second contact pads is formed over a second surface of the substrate. A dummy pattern is formed over the second surface of the substrate. An indentation is formed in a sidewall of the substrate. An opening is formed through the substrate. An encapsulant is deposited in the opening. An insulating layer is formed over second surface of the substrate. A dummy opening is formed in the insulating layer. A semiconductor die is disposed adjacent to the substrate. An encapsulant is deposited over the semiconductor die and substrate. The first surface of the substrate includes a width that is greater than a width of the second surface of the substrate.

First claim

What is claimed:

1. A method of making a semiconductor device, comprising:
providing a carrier;
providing a substrate;
forming a first conductive layer over a first surface of the substrate;
forming a second conductive layer over a second surface of the substrate, the second conductive layer including a dummy pattern to approximately balance the second conductive layer with the first conductive layer;
disposing the substrate on the carrier;
disposing a semiconductor die on the carrier laterally offset from the substrate; and
depositing an encapsulant over the carrier between a side surface of the semiconductor die and a side surface of the substrate that opposes the side surface of the semiconductor die.

2. The method of claim 1 , further including forming an indentation in a sidewall of the substrate.

3. The method of claim 1 , further including forming an opening through the substrate.

4. The method of claim 3 , further including depositing an encapsulant in the opening of the substrate.

5. The method of claim 1 , further including:
forming an insulating layer over the second surface of the substrate; and
forming a dummy opening in the insulating layer.

6. The method of claim 1 , wherein the first surface of the substrate includes a width that is greater than a width of the second surface of the substrate.

7. A semiconductor device, comprising:
a carrier;
a substrate disposed on the carrier, the substrate including,
a first conductive layer formed over a first surface of the substrate, and
a second conductive layer formed over a second surface of the substrate, the second conductive layer including a dummy pattern to approximately balance the second conductive layer with the first conductive layer;

a semiconductor die disposed on the carrier laterally offset from the substrate; and
an encapsulant deposited over the carrier between a side surface of the semiconductor die and a side surface of the substrate that opposes the side surface of the semiconductor die.

8. The semiconductor device of claim 7 , wherein a sidewall of the substrate includes an indentation.

9. The semiconductor device of claim 7 , wherein the substrate includes an opening.

10. The semiconductor device of claim 9 , wherein the encapsulant is disposed in the opening of the substrate.

11. The semiconductor device of claim 7 , wherein the first surface of the substrate includes a width greater than a width of the second surface of the substrate.

12. A semiconductor device, comprising:
a substrate including a conductive via formed through the substrate;
a first conductive layer formed over a first surface area of a first surface of the substrate including over the conductive via;
a second conductive layer formed over a second surface area of a second surface of the substrate including over the conductive via;
a dummy conductive pattern formed over a third surface area of the first surface of the substrate, wherein a sum of the first surface area and third surface area is approximately equal to the second surface area;
a first insulating layer formed over the first surface of the substrate with an opening in the first insulating layer over the first conductive layer; and
a second insulating layer formed over the second surface of the substrate with a first opening in the second insulating layer over the second conductive layer and a dummy opening in the second insulating layer outside a footprint of the second conductive layer, wherein the dummy opening is configured to balance a first weight of the first insulating layer with a second weight of the second insulating layer.

13. The semiconductor device of claim 12 , wherein a sidewall of the substrate includes an indentation.

14. The semiconductor device of claim 12 , wherein the substrate includes an opening.

15. The semiconductor device of claim 14 , further including an encapsulant disposed in the opening of the substrate.

16. The semiconductor device of claim 12 , wherein the substrate includes a molding compound.

17. The semiconductor device of claim 12 , further including:
a semiconductor die disposed adjacent to the substrate; and
an encapsulant deposited between opposing side surfaces of the semiconductor die and substrate.

18. A semiconductor device, comprising:
a substrate;
a plurality of first contact pads formed over a first surface of the substrate;
a plurality of second contact pads formed over a second surface of the substrate; and
a dummy pattern formed over the second surface of the substrate, wherein an area of the first surface covered by the first contact pads is approximately equal to an area of the second surface covered by the second contact pads plus an area of the dummy pattern.

19. The semiconductor device of claim 18 , wherein a sidewall of the substrate includes an indentation.

20. The semiconductor device of claim 18 , further including an opening through the substrate.

21. The semiconductor device of claim 20 , further including an encapsulant disposed in the opening of the substrate.

22. The semiconductor device of claim 18 , further including an insulating layer formed over the second surface of the substrate with a dummy opening in the insulating layer.

23. The semiconductor device of claim 18 , further including:
a semiconductor die disposed adjacent to the substrate; and
an encapsulant disposed over the semiconductor die and substrate.

Assignees

• Stats Chippac Ltd
• Stats Chippac Pte Ltd

Inventors

• Lin Yaojian
• Chen Kang
• Goh Hin Hwa
• Shim Ii Kwon

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title